Patchwork [ARM,7/n] Comment on splitting THUMB1 patterns

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Submitter Greta Yorsh
Date Feb. 18, 2013, 6:46 p.m.
Message ID <002b01ce0e08$364fa6c0$a2eef440$@yorsh@arm.com>
Download mbox | patch
Permalink /patch/221448/
State New
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Comments

Greta Yorsh - Feb. 18, 2013, 6:46 p.m.
This patch adds a comment explaining why it is difficult to split Thumb1
patterns.

gcc/

2013-02-12  Greta Yorsh  <Greta.Yorsh@arm.com>

   * config/arm/arm.md: Comment on splitting Thumb1 patterns.

Patch

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 64888f9..ce98013 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -22,6 +22,25 @@ 
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
+;; Beware of splitting Thumb1 patterns that output multiple
+;; assembly instructions, in particular instruction such as SBC and
+;; ADC which consume flags.  For example, in the pattern thumb_subdi3
+;; below, the output SUB implicitly sets the flags (assembled to SUBS)
+;; and then the Carry flag is used by SBC to compute the correct
+;; result.  If we split thumb_subdi3 pattern into two separate RTL
+;; insns (using define_insn_and_split), the scheduler might place
+;; other RTL insns between SUB and SBC, possibly modifying the Carry
+;; flag used by SBC.  This might happen because most Thumb1 patterns
+;; for flag-setting instructions do not have explicit RTL for setting
+;; or clobbering the flags.  Instead, they have the attribute "conds"
+;; with value "set" or "clob".  However, this attribute is not used to
+;; identify dependencies and therefore the scheduler might reorder
+;; these instruction.  Currenly, this problem cannot happen because
+;; there are no separate Thumb1 patterns for individual instruction
+;; that consume flags (except conditional execution, which is treated
+;; differently).  In particular there is no Thumb1 armv6-m pattern for
+;; sbc or adc.
+
 
 ;;---------------------------------------------------------------------------
 ;; Constants