Patchwork [SeaBIOS,edk2] (PAM stuff) reset doesn't work on OVMF + SeaBIOS CSM

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Submitter Kevin O'Connor
Date Feb. 18, 2013, 5:44 p.m.
Message ID <20130218174459.GA21352@morn.localdomain>
Download mbox | patch
Permalink /patch/221425/
State New
Headers show

Comments

Kevin O'Connor - Feb. 18, 2013, 5:44 p.m.
On Mon, Feb 18, 2013 at 06:12:55PM +0100, Laszlo Ersek wrote:
> On 02/18/13 13:53, David Woodhouse wrote:
> I single-stepped qemu-1.3.1 in x86_cpu_reset() /
> cpu_x86_load_seg_cache(), and we seem to set the correct base. However
> when I pause the VM when it's spinning in the reset loop, and I issue
> the following in virsh:
[...]
> EIP=0000fff0 EFL=00000002 [-------] CPL=3 II=0 A20=1 SMM=0 HLT=0
> ES =0000 00000000 0000ffff 0000f300
> CS =f000 000f0000 0000ffff 0000f300

If you're seeing the CPU running at 0x000ffff0 then that would
certainly be wrong.  It needs to run at 0xfffffff0.  Maybe this has
something to do with KVM's difficulty with executing in "big real"
mode?

Just to verify this is a cpu eip issue and not a memory mapping issue,
one could try applying the patch below to seabios.  On a working
system during a reboot the patch should report "before val=1/0" and
"after val=2/0" (the second value could be anything, but should not
change).  If you do see the second value changing it would indicate
memory mapping issues.

-Kevin

Patch

--- a/src/resume.c
+++ b/src/resume.c
@@ -129,6 +129,12 @@  tryReboot(void)
 {
     dprintf(1, "Attempting a hard reboot\n");
 
+    dprintf(1, "before val=%x/%x\n", HaveRunPost, *(int*)((void*)&HaveRunPost + 0xfff00000));
+    barrier();
+    HaveRunPost = 2;
+    barrier();
+    dprintf(1, "after val=%x/%x\n", HaveRunPost, *(int*)((void*)&HaveRunPost + 0xfff00000));
+
     // Setup for reset on qemu.
     qemu_prep_reset();