From patchwork Mon Feb 18 00:45:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Otavio Salvador X-Patchwork-Id: 221127 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1ACE02C0082 for ; Mon, 18 Feb 2013 11:41:46 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD57B4A89C; Mon, 18 Feb 2013 01:41:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iTQDOJE1RycM; Mon, 18 Feb 2013 01:41:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5A52A4A861; Mon, 18 Feb 2013 01:41:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F5C04A7DD for ; Mon, 18 Feb 2013 01:41:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5FbvpHcLGQDE for ; Mon, 18 Feb 2013 01:41:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f172.google.com (mail-gg0-f172.google.com [209.85.161.172]) by theia.denx.de (Postfix) with ESMTPS id 9B30C4A7D8 for ; Mon, 18 Feb 2013 01:41:15 +0100 (CET) Received: by mail-gg0-f172.google.com with SMTP id f4so829635ggn.3 for ; Sun, 17 Feb 2013 16:41:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=3PKTVxcXLhmCs3VPdUxRg3DyTJpe5/g0FWs2HO9NLRo=; b=COdRUZ2o07zY1YFJXwHWWCRzyACXfMHmhiLHYy7r4aEHkaZoiV+hzDS6tcHzCIj/me wKsjhmAmAzZD9u1hgoIiGQZrmIqXVcmuGuZinIavfvhV5VxCcWjyN9RLDoQnRubXGjxB tcbgNe7jHV/5cMyCifsJ7RtcewhCi9jeS68DNf1Pinob9cJRcR/+VlFLAcJKnwFJwAC7 40lgD2jSa2knyrydMNZ0SIJiJ8YTKCB68IHsVFe2TSepgX6n8NFY/v7sP04w1OqOwQ8l ZBCdRufxhqX4nfnW82j2riJDlZI6DxC6b4TKfdC6gFbX3IKrkM5C+D9xnjDQqGA6qWDG phGA== X-Received: by 10.101.16.2 with SMTP id t2mr4908316ani.6.1361148074620; Sun, 17 Feb 2013 16:41:14 -0800 (PST) Received: from nano.lab.ossystems.com.br ([187.23.144.59]) by mx.google.com with ESMTPS id j1sm111429376yhn.3.2013.02.17.16.41.11 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Feb 2013 16:41:13 -0800 (PST) From: Otavio Salvador To: U-Boot Mailing List Date: Sun, 17 Feb 2013 21:45:27 -0300 Message-Id: <1361148335-19197-3-git-send-email-otavio@ossystems.com.br> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1361148335-19197-1-git-send-email-otavio@ossystems.com.br> References: <1361148335-19197-1-git-send-email-otavio@ossystems.com.br> Cc: Fabio Estevam , Marek Vasut , Otavio Salvador Subject: [U-Boot] [PATCH v4 02/10] mx23: Document the tRAS lockout setting in memory initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to enable the 'Fast Auto Pre-Charge' found in the memory chip. The setting is applied after memory initialization and it is worth document it. Signed-off-by: Otavio Salvador --- Changes in v4: None Changes in v3: - Extend code comment to be more verbose (Marek) Changes in v2: - Extend code comment to explicit say it needs to be there. arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..4db9baa 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -119,6 +119,10 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* + * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last + * element to be set + */ writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); #endif }