From patchwork Sun Feb 17 19:45:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Otavio Salvador X-Patchwork-Id: 221097 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 65BFB2C007A for ; Mon, 18 Feb 2013 06:42:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 62E9D4A17F; Sun, 17 Feb 2013 20:41:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 48NuaUAG3ngK; Sun, 17 Feb 2013 20:41:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4B8304A10D; Sun, 17 Feb 2013 20:41:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFB624A0F6 for ; Sun, 17 Feb 2013 20:41:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UKr3zbTqC-Ap for ; Sun, 17 Feb 2013 20:41:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f42.google.com (mail-yh0-f42.google.com [209.85.213.42]) by theia.denx.de (Postfix) with ESMTPS id 5B5F54A0FF for ; Sun, 17 Feb 2013 20:41:02 +0100 (CET) Received: by mail-yh0-f42.google.com with SMTP id w49so880137yhw.29 for ; Sun, 17 Feb 2013 11:41:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=DkRmLFzQBYQ9+1xolZg5dlNu0+L11DVl+093tIS8/nM=; b=VLU7pTEB7xOpCWhAOxrF4SqGMiBNutoViq8Z4bMavBObMpAUSn6rtrh6/AUqFW/zcv rlr1euJhl1WvYJuN9PtLP7txJvJPvv/nKpJGgezYkzFK6rzF0qoqEiSP9VWyi+KXSZjM 5vm9NQ56vCLMMjqOnGnF4a+ypF8APZBSFEHDaigHXhFd88H1Y3mWu7S41ZLrUz7Fp1CV Di9btmpWvUBcaFlwQ9wNQzfgj5Bs2swCTkGrtV0qJnDqfAtcUKgZSsV918qb9/WMwVZw v2VjfuueaW7WnDj0/8prwCZ5RpEGuupW5zpjVvzr1sr034SAW1RBXu54TL/knt4fzC8I pdWg== X-Received: by 10.236.130.98 with SMTP id j62mr16203453yhi.119.1361130061295; Sun, 17 Feb 2013 11:41:01 -0800 (PST) Received: from nano.lab.ossystems.com.br ([187.23.144.59]) by mx.google.com with ESMTPS id n4sm26667009ank.1.2013.02.17.11.40.58 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Feb 2013 11:41:00 -0800 (PST) From: Otavio Salvador To: U-Boot Mailing List Date: Sun, 17 Feb 2013 16:45:21 -0300 Message-Id: <1361130325-5202-8-git-send-email-otavio@ossystems.com.br> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1361130325-5202-1-git-send-email-otavio@ossystems.com.br> References: <1361130325-5202-1-git-send-email-otavio@ossystems.com.br> Cc: Marek Vasut , Fabio Estevam , Otavio Salvador Subject: [U-Boot] [PATCH v3 07/10] usb: mxs: Adapt code for i.MX23 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The i.MX23 just one USB port so we shouldn't mess up with PLL1CTRL and USB1 port when building for i.MX23. Signed-off-by: Otavio Salvador --- Changes in v3: - Improve commit log - Move code to enable/disable clock to soc_ehci_hcd_{enable,disable}_clock - Proper use mx23 clock registers Changes in v2: - Avoid wrong clock setting in MX23 drivers/usb/host/ehci-mxs.c | 78 ++++++++++++++++++++++++++++++++------------- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 5062af5..5e41a38 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -23,7 +23,11 @@ #include #include #include +#if defined(CONFIG_MX23) +#include +#elif defined(CONFIG_MX28) #include +#endif #include #include @@ -50,10 +54,12 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) usb_base = MXS_USBCTRL0_BASE; phy_base = MXS_USBPHY0_BASE; break; +#ifdef CONFIG_MX28 case 1: usb_base = MXS_USBCTRL1_BASE; phy_base = MXS_USBPHY1_BASE; break; +#endif default: printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port); return -1; @@ -67,18 +73,63 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) /* This DIGCTL register ungates clock to USB */ #define HW_DIGCTL_CTRL 0x8001c000 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) +#ifdef CONFIG_MX28 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) +#endif -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +static void soc_ehci_hcd_enable_clock(void) { + struct mxs_register_32 *digctl_ctrl = + (struct mxs_register_32 *)HW_DIGCTL_CTRL; + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - int ret; - uint32_t usb_base, cap_base; +#if defined(CONFIG_MX23) + writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + + writel(HW_DIGCTL_CTRL_USB0_CLKGATE, &digctl_ctrl->reg_clr); +#elif defined(CONFIG_MX28) + writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll1ctrl0_set); + + writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, + &digctl_ctrl->reg_clr); +#endif +} + +static void soc_ehci_hcd_disable_clock(void) +{ struct mxs_register_32 *digctl_ctrl = (struct mxs_register_32 *)HW_DIGCTL_CTRL; struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; +#if defined(CONFIG_MX23) + writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr); + + /* Gate off the USB clock */ + writel(HW_DIGCTL_CTRL_USB0_CLKGATE, &digctl_ctrl->reg_set); +#elif defined(CONFIG_MX28) + writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr); + writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS, + &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr); + + /* Gate off the USB clock */ + writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, + &digctl_ctrl->reg_set); +#endif +} + +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + uint32_t usb_base, cap_base; + ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT); if (ret) return ret; @@ -90,13 +141,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr); /* Enable USB clock */ - writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll1ctrl0_set); - - writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, - &digctl_ctrl->reg_clr); + soc_ehci_hcd_enable_clock(); /* Start USB PHY */ writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd); @@ -118,10 +163,6 @@ int ehci_hcd_stop(int index) { int ret; uint32_t usb_base, cap_base, tmp; - struct mxs_register_32 *digctl_ctrl = - (struct mxs_register_32 *)HW_DIGCTL_CTRL; - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct ehci_hccr *hccr; struct ehci_hcor *hcor; @@ -147,14 +188,7 @@ int ehci_hcd_stop(int index) writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd); /* Disable USB clock */ - writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr); - writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS, - &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr); - - /* Gate off the USB clock */ - writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, - &digctl_ctrl->reg_set); + soc_ehci_hcd_disable_clock(); return 0; }