From patchwork Sat Feb 16 12:19:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julio Guerra X-Patchwork-Id: 220957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 468E82C007B for ; Sat, 16 Feb 2013 23:28:07 +1100 (EST) Received: from localhost ([::1]:59107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6gs9-0001Ly-BH for incoming@patchwork.ozlabs.org; Sat, 16 Feb 2013 07:28:05 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6gs0-0001Lg-5b for qemu-devel@nongnu.org; Sat, 16 Feb 2013 07:27:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U6gry-0008Ez-CN for qemu-devel@nongnu.org; Sat, 16 Feb 2013 07:27:56 -0500 Received: from mail-we0-x230.google.com ([2a00:1450:400c:c03::230]:38033) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6gry-0008Ec-3i; Sat, 16 Feb 2013 07:27:54 -0500 Received: by mail-we0-f176.google.com with SMTP id s43so3455152wey.21 for ; Sat, 16 Feb 2013 04:27:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:mime-version:sender:from:date:x-google-sender-auth :message-id:subject:to:content-type; bh=b2zWe7I8xVcnZSv+62+Ed5bg1EEsworO3p89FewT6Sg=; b=v2sZ5VGV5T4YgG/dYXWywPuf3PXq8qn0mG9I9lw0cIMpftKaR/1jpKvzqjLloYUeVI Qb9TTJdJJggZzU44m9JQvxcmnRPf2n7m4Ku24src89oy2TBfSgRWHL9WRHPdMOCuj+zb GDw6lqYGUqksa6dOonROcAMRlfx72lCcwhmViDl+8ALaOXLEkRLpuZAQ2ygN/OmHQxYb U50TP1gpPFEEGGZ4Nqg6Ej+7ibbdqjKOdP1PoVepF72tUjdUFFV4hCWXLHDx6ScDQqcI 2ZxUTf/FiBOkBQpWlmqzny+CgQZimmHTOvIve8sHPIdRvYcH6/u2+BX9rBsFhyZoyjfQ ISlw== X-Received: by 10.180.79.201 with SMTP id l9mr9067206wix.20.1361017179257; Sat, 16 Feb 2013 04:19:39 -0800 (PST) MIME-Version: 1.0 Received: by 10.180.36.136 with HTTP; Sat, 16 Feb 2013 04:19:19 -0800 (PST) From: Julio Guerra Date: Sat, 16 Feb 2013 13:19:19 +0100 X-Google-Sender-Auth: S79y7M1oMHW5GxUH9WvYSKKl6To Message-ID: To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Alexander Graf X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c03::230 Subject: [Qemu-devel] [PATCH] PReP Software Reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The software reset of a PReP machine should reset the entire system and not only the processor. It occurs when changing the 7th bit of port 0092 from 0 to 1. Adding a new variable in PReP's sysctrl_t to store the soft reset bit makes possible to be compliant with PReP specification : * reset the system when changing soft reset bit from 0 to 1. * the soft reset bit value is 1 after a soft reset. * Port 0092 is read/write. qemu_system_reset_request() does the required job (calling the reset handlers) when the software reset is needed. reset_irq is no longer needed, the CPU reset (calling ppc_prep_reset) is called when qemu_system_reset calls every reset handlers. Signed-off-by: Julio Guerra --- prep.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) if (val & 0x02) { @@ -267,7 +269,7 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) switch (addr) { case 0x0092: /* Special port 92 */ - retval = 0x00; + retval = (sysctrl->endian << 1) | sysctrl->sreset; break; case 0x0800: /* Motorola CPU configuration register */ @@ -624,7 +626,8 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) } isa_create_simple(isa_bus, "i8042"); - sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; + sysctrl->sreset = 0; + sysctrl->endian = 0; /* System control ports */ register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index e06dded..64dab8b 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -178,12 +178,12 @@ static const MemoryRegionOps PPC_XCSR_ops = { /* Fake super-io ports for PREP platform (Intel 82378ZB) */ typedef struct sysctrl_t { - qemu_irq reset_irq; M48t59State *nvram; uint8_t state; uint8_t syscontrol; int contiguous_map; int endian; + uint8_t sreset; } sysctrl_t; enum { @@ -203,9 +203,11 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) /* Special port 92 */ /* Check soft reset asked */ if (val & 0x01) { - qemu_irq_raise(sysctrl->reset_irq); + if (!sysctrl->sreset) + qemu_system_reset_request(); + sysctrl->sreset = 1; } else { - qemu_irq_lower(sysctrl->reset_irq); + sysctrl->sreset = 0; } /* Check LE mode */