From patchwork Fri Feb 15 21:11:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 220871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0C48E2C0089 for ; Sat, 16 Feb 2013 08:11:48 +1100 (EST) Received: from localhost ([::1]:46162 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6SZO-0000QJ-NP for incoming@patchwork.ozlabs.org; Fri, 15 Feb 2013 16:11:46 -0500 Received: from eggs.gnu.org ([208.118.235.92]:46619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6SZG-0000Q5-Jb for qemu-devel@nongnu.org; Fri, 15 Feb 2013 16:11:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U6SZF-0005Es-64 for qemu-devel@nongnu.org; Fri, 15 Feb 2013 16:11:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:22848) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U6SZE-0005Em-Tb for qemu-devel@nongnu.org; Fri, 15 Feb 2013 16:11:37 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r1FLBaEc023839 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 15 Feb 2013 16:11:36 -0500 Received: from bling.home (ovpn-113-86.phx2.redhat.com [10.3.113.86]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id r1FLBZWc008653; Fri, 15 Feb 2013 16:11:36 -0500 To: seabios@seabios.org From: Alex Williamson Date: Fri, 15 Feb 2013 14:11:35 -0700 Message-ID: <20130215211135.5990.10249.stgit@bling.home> In-Reply-To: <20130215210807.5990.82992.stgit@bling.home> References: <20130215210807.5990.82992.stgit@bling.home> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [RESEND PATCH v2 1/2] seabios q35: Enable all PIRQn IRQs at startup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We seem to use the IRQEN bit of the PIRQn registers interchangeably to select APIC mode or to disable an IRQ. I can't decide if we're intending to disable the IRQ or select APIC mode here, but in either case it prevents PIC mode assigned devices from working. When seabios writes IRQEN to these registers, qemu interprets that as APIC mode, so while the boot ROM driver is waiting for an interrupt on ISA compatible IRQ 10 or 11, KVM is injecting interrupts to APIC pins 16 - 23. Devices on the root bus use PIRQE:H while the root ports use PIRQA:D. Enable them all so we don't limit where we support boot ROMs. The guest will later disable unused IRQs with the ACPI _DIS method. Signed-off-by: Alex Williamson --- src/pciinit.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 1d34653..05c0fe8 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -143,11 +143,9 @@ void mch_isa_bridge_setup(struct pci_device *dev, void *arg) /* activate irq remapping in LPC */ /* PIRQ[A-D] routing */ - pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, - irq | ICH9_LPC_PIRQ_ROUT_IRQEN); + pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq); /* PIRQ[E-H] routing */ - pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, - irq | ICH9_LPC_PIRQ_ROUT_IRQEN); + pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq); } outb(elcr[0], ICH9_LPC_PORT_ELCR1); outb(elcr[1], ICH9_LPC_PORT_ELCR2);