From patchwork Fri Feb 15 12:36:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 220733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 532052C0092 for ; Fri, 15 Feb 2013 23:44:27 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935862Ab3BOMoM (ORCPT ); Fri, 15 Feb 2013 07:44:12 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:9493 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935797Ab3BOMoK (ORCPT ); Fri, 15 Feb 2013 07:44:10 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 15 Feb 2013 04:43:58 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 15 Feb 2013 04:40:04 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 15 Feb 2013 04:40:04 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.297.1; Fri, 15 Feb 2013 04:44:07 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Fri, 15 Feb 2013 04:44:07 -0800 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r1FCccpi014652; Fri, 15 Feb 2013 04:44:03 -0800 (PST) From: Peter De Schrijver To: Peter De Schrijver CC: , , Grant Likely , Rob Herring , Rob Landley , Stephen Warren , Russell King , Prashant Gaikwad , Simon Glass , Mike Turquette , Joseph Lo , , , Subject: [PATCH v7 07/12] clk: tegra: Workaround for Tegra114 MSENC problem Date: Fri, 15 Feb 2013 14:36:37 +0200 Message-ID: <1360931849-7090-8-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com> References: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c | 9 +++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 6dd5332..c9083fb 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); #define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32)) +#define LVL2_CLK_GATE_OVRE 0x554 + /* Peripheral gate clock ops */ static int clk_periph_is_enabled(struct clk_hw *hw) { @@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw) } } + if (gate->flags & TEGRA_PERIPH_WAR_1005168) { + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); + udelay(1); + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); + } + spin_unlock_irqrestore(&periph_ref_lock, flags); return 0; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 4c4bf9a..fa21c88 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -356,6 +356,7 @@ struct tegra_clk_periph_regs { * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the * bus to flush the write operation in apb bus. This flag indicates * that this peripheral is in apb bus. + * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug */ struct tegra_clk_periph_gate { u32 magic; @@ -375,6 +376,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_NO_RESET BIT(0) #define TEGRA_PERIPH_MANUAL_RESET BIT(1) #define TEGRA_PERIPH_ON_APB BIT(2) +#define TEGRA_PERIPH_WAR_1005168 BIT(3) void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); extern const struct clk_ops tegra_clk_periph_gate_ops;