Patchwork [1/5,net-next] tg3: Add 57766 device support.

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Submitter Michael Chan
Date Feb. 14, 2013, 10:13 p.m.
Message ID <1360880022-12856-1-git-send-email-mchan@broadcom.com>
Download mbox | patch
Permalink /patch/220532/
State Superseded
Delegated to: David Miller
Headers show

Comments

Michael Chan - Feb. 14, 2013, 10:13 p.m.
From: Matt Carlson <mcarlson@broadcom.com>

The patch also adds a couple of fixes

 - For the 57766, bootcode needs to setup the PCIE Fast Training
   Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
   does not have enough room in the selfboot case (i.e. devices with no
   NVRAM).  The driver needs to implement this.

 - For performance reasons, the 2k DMA engine mode on the 57766 should
   be enabled and dma size limited to 2k for standard sized packets.

Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
 drivers/net/ethernet/broadcom/tg3.c |   18 +++++++++++++++++-
 drivers/net/ethernet/broadcom/tg3.h |    2 ++
 2 files changed, 19 insertions(+), 1 deletions(-)
Joe Perches - Feb. 14, 2013, 10:25 p.m.
On Thu, 2013-02-14 at 14:13 -0800, Michael Chan wrote:
> From: Matt Carlson <mcarlson@broadcom.com>
> 
> The patch also adds a couple of fixes
> 
>  - For the 57766, bootcode needs to setup the PCIE Fast Training
>    Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
>    does not have enough room in the selfboot case (i.e. devices with no
>    NVRAM).  The driver needs to implement this.
[]
> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
[]
> @@ -9179,7 +9180,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
>  		}
>  
>  		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
> -			u32 grc_mode = tr32(GRC_MODE);
> +			u32 grc_mode;
> +
> +			/* Fix transmit hangs */
> +			val = tr32(TG3_CPMU_PADRNG_CTL);
> +			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
> +			tw32(TG3_CPMU_PADRNG_CTL, val);
> +

This seems to write this val to more devices than just
a 57766.  Intentional?

> +			grc_mode = tr32(GRC_MODE);
>  
>  			/* Access the lower 1K of DL PCIE block registers. */
>  			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;


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Nithin Sujir - Feb. 14, 2013, 11:13 p.m.
On 02/14/2013 02:25 PM, Joe Perches wrote:
> On Thu, 2013-02-14 at 14:13 -0800, Michael Chan wrote:
>> From: Matt Carlson <mcarlson@broadcom.com>
>>
>> The patch also adds a couple of fixes
>>
>>   - For the 57766, bootcode needs to setup the PCIE Fast Training
>>     Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
>>     does not have enough room in the selfboot case (i.e. devices with no
>>     NVRAM).  The driver needs to implement this.
> []
>> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
> []
>> @@ -9179,7 +9180,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
>>   		}
>>
>>   		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
>> -			u32 grc_mode = tr32(GRC_MODE);
>> +			u32 grc_mode;
>> +
>> +			/* Fix transmit hangs */
>> +			val = tr32(TG3_CPMU_PADRNG_CTL);
>> +			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
>> +			tw32(TG3_CPMU_PADRNG_CTL, val);
>> +
>
> This seems to write this val to more devices than just
> a 57766.  Intentional?
>

Yes. In addition to the 57766, this fix applies to non-AX revisions of the 57765.

It's not apparent from the patch, but this code chunk is inside the conditional -

	if (tg3_flag(tp, 57765_CLASS)) {

which is set for 57765 and 57766 devices.



>> +			grc_mode = tr32(GRC_MODE);
>>
>>   			/* Access the lower 1K of DL PCIE block registers. */
>>   			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
>
>
>

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Joe Perches - Feb. 14, 2013, 11:16 p.m.
On Thu, 2013-02-14 at 15:13 -0800, Nithin Nayak Sujir wrote:
> 
> On 02/14/2013 02:25 PM, Joe Perches wrote:
> > On Thu, 2013-02-14 at 14:13 -0800, Michael Chan wrote:
> >> From: Matt Carlson <mcarlson@broadcom.com>
> >>
> >> The patch also adds a couple of fixes
> >>
> >>   - For the 57766, bootcode needs to setup the PCIE Fast Training
> >>     Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
> >>     does not have enough room in the selfboot case (i.e. devices with no
> >>     NVRAM).  The driver needs to implement this.
> > []
> >> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
> > []
> >> @@ -9179,7 +9180,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
> >>   		}
> >>
> >>   		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
> >> -			u32 grc_mode = tr32(GRC_MODE);
> >> +			u32 grc_mode;
> >> +
> >> +			/* Fix transmit hangs */
> >> +			val = tr32(TG3_CPMU_PADRNG_CTL);
> >> +			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
> >> +			tw32(TG3_CPMU_PADRNG_CTL, val);
> >> +
> >
> > This seems to write this val to more devices than just
> > a 57766.  Intentional?
> >
> 
> Yes. In addition to the 57766, this fix applies to non-AX revisions of the 57765.
> 
> It's not apparent from the patch, but this code chunk is inside the conditional -
> 
> 	if (tg3_flag(tp, 57765_CLASS)) {
> 
> which is set for 57765 and 57766 devices.

I know. 

The commit message does not describe the patch correctly.
The commit message says "for the 57766".


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Patch

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index b1b3bc0..6e676a7 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -332,6 +332,7 @@  static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
+	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
 	{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
@@ -9179,7 +9180,14 @@  static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 		}
 
 		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
-			u32 grc_mode = tr32(GRC_MODE);
+			u32 grc_mode;
+
+			/* Fix transmit hangs */
+			val = tr32(TG3_CPMU_PADRNG_CTL);
+			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
+			tw32(TG3_CPMU_PADRNG_CTL, val);
+
+			grc_mode = tr32(GRC_MODE);
 
 			/* Access the lower 1K of DL PCIE block registers. */
 			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
@@ -9492,6 +9500,14 @@  static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 	if (tg3_flag(tp, PCI_EXPRESS))
 		rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
 
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
+		tp->dma_limit = 0;
+		if (tp->dev->mtu <= ETH_DATA_LEN) {
+			rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
+			tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
+		}
+	}
+
 	if (tg3_flag(tp, HW_TSO_1) ||
 	    tg3_flag(tp, HW_TSO_2) ||
 	    tg3_flag(tp, HW_TSO_3))
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index ef6ced2..b676728 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1164,6 +1164,8 @@ 
 #define  CPMU_MUTEX_GNT_DRIVER		 0x00001000
 #define TG3_CPMU_PHY_STRAP		0x00003664
 #define TG3_CPMU_PHY_STRAP_IS_SERDES	 0x00000020
+#define TG3_CPMU_PADRNG_CTL		0x00003668
+#define  TG3_CPMU_PADRNG_CTL_RDIV2	 0x00040000
 /* 0x3664 --> 0x36b0 unused */
 
 #define TG3_CPMU_EEE_MODE		0x000036b0