Patchwork [U-Boot,v2,1/5] x86: Remove eNET boards

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Submitter Simon Glass
Date Feb. 14, 2013, 2:18 p.m.
Message ID <1360851535-23805-2-git-send-email-sjg@chromium.org>
Download mbox | patch
Permalink /patch/220452/
State Accepted, archived
Delegated to: Simon Glass
Headers show

Comments

Simon Glass - Feb. 14, 2013, 2:18 p.m.
These are no longer used and should be removed.


Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
---
Changes in v2: None

 board/eNET/Makefile       |  52 ----
 board/eNET/eNET.c         | 284 ---------------------
 board/eNET/eNET_pci.c     | 128 ----------
 board/eNET/eNET_start.S   |  30 ---
 board/eNET/eNET_start16.S |  87 -------
 board/eNET/hardware.h     |  36 ---
 boards.cfg                |   2 -
 include/configs/eNET.h    | 619 ----------------------------------------------
 8 files changed, 1238 deletions(-)
 delete mode 100644 board/eNET/Makefile
 delete mode 100644 board/eNET/eNET.c
 delete mode 100644 board/eNET/eNET_pci.c
 delete mode 100644 board/eNET/eNET_start.S
 delete mode 100644 board/eNET/eNET_start16.S
 delete mode 100644 board/eNET/hardware.h
 delete mode 100644 include/configs/eNET.h
Gabe Black - Feb. 14, 2013, 11:58 p.m.
Acked-by: Gabe Black <gabeblack@chromium.org>


On Thu, Feb 14, 2013 at 6:18 AM, Simon Glass <sjg@chromium.org> wrote:

> These are no longer used and should be removed.
>
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Graeme Russ <graeme.russ@gmail.com>
> ---
> Changes in v2: None
>
>  board/eNET/Makefile       |  52 ----
>  board/eNET/eNET.c         | 284 ---------------------
>  board/eNET/eNET_pci.c     | 128 ----------
>  board/eNET/eNET_start.S   |  30 ---
>  board/eNET/eNET_start16.S |  87 -------
>  board/eNET/hardware.h     |  36 ---
>  boards.cfg                |   2 -
>  include/configs/eNET.h    | 619
> ----------------------------------------------
>  8 files changed, 1238 deletions(-)
>  delete mode 100644 board/eNET/Makefile
>  delete mode 100644 board/eNET/eNET.c
>  delete mode 100644 board/eNET/eNET_pci.c
>  delete mode 100644 board/eNET/eNET_start.S
>  delete mode 100644 board/eNET/eNET_start16.S
>  delete mode 100644 board/eNET/hardware.h
>  delete mode 100644 include/configs/eNET.h
>
> diff --git a/board/eNET/Makefile b/board/eNET/Makefile
> deleted file mode 100644
> index ad1c5b1..0000000
> --- a/board/eNET/Makefile
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -#
> -# (C) Copyright 2008
> -# Graeme Russ, graeme.russ@gmail.com.
> -#
> -# (C) Copyright 2006
> -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
> -#
> -# (C) Copyright 2002
> -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -
> -include $(TOPDIR)/config.mk
> -
> -LIB    = $(obj)lib$(BOARD).o
> -
> -COBJS-y        += eNET.o
> -COBJS-$(CONFIG_PCI) += eNET_pci.o
> -SOBJS-y        += eNET_start16.o
> -SOBJS-y        += eNET_start.o
> -
> -SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> -OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
> -
> -$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
> -       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> -
> -#########################################################################
> -
> -# defines $(obj).depend target
> -include $(SRCTREE)/rules.mk
> -
> -sinclude $(obj).depend
> -
> -#########################################################################
> diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
> deleted file mode 100644
> index 2f26470..0000000
> --- a/board/eNET/eNET.c
> +++ /dev/null
> @@ -1,284 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Graeme Russ, graeme.russ@gmail.com.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <asm/io.h>
> -#include <asm/arch/sc520.h>
> -#include <net.h>
> -#include <netdev.h>
> -
> -#ifdef CONFIG_HW_WATCHDOG
> -#include <watchdog.h>
> -#endif
> -
> -#include "hardware.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
> -
> -static void enet_timer_isr(void);
> -static void enet_toggle_run_led(void);
> -static void enet_setup_pars(void);
> -
> -/*
> - * Miscellaneous platform dependent initializations
> - */
> -int board_early_init_f(void)
> -{
> -       u16 pio_out_cfg = 0x0000;
> -
> -       /* Configure General Purpose Bus timing */
> -       writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
> -       writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
> -       writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
> -       writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
> -       writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
> -       writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
> -       writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
> -
> -       /* Configure Programmable Input/Output Pins */
> -       writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
> -       writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
> -       writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
> -       writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
> -       writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
> -       writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
> -
> -       /*
> -        * Turn off top board
> -        * Set StrataFlash chips to 16-bit width
> -        * Set StrataFlash chips to normal (non reset/power down) mode
> -        */
> -       pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
> -       pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
> -       pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
> -       pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
> -       writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
> -
> -       /* Turn off auxiliary power output */
> -       writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
> -
> -       /* Clear FPGA program mode */
> -       writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
> -
> -       enet_setup_pars();
> -
> -       /* Disable Watchdog */
> -       writew(0x3333, &sc520_mmcr->wdtmrctl);
> -       writew(0xcccc, &sc520_mmcr->wdtmrctl);
> -       writew(0x0000, &sc520_mmcr->wdtmrctl);
> -
> -       /* Chip Select Configuration */
> -       writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
> -       writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
> -       writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
> -
> -       writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
> -       writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
> -       writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
> -
> -       writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
> -       writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
> -
> -       /* enable posted-writes */
> -       writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
> -
> -       return 0;
> -}
> -
> -static void enet_setup_pars(void)
> -{
> -       /*
> -        * PARs 11 and 12 are 2MB SRAM @ 0x19000000
> -        *
> -        * These are setup now because older version of U-Boot have them
> -        * mapped to a different PAR which gets clobbered which prevents
> -        * using SRAM for warm-booting a new image
> -        */
> -       writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
> -       writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
> -
> -       /* PARs 0 and 1 are Compact Flash slots (4kB each) */
> -       writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
> -       writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
> -
> -       /* PAR 2 is used for Cache-As-RAM */
> -
> -       /*
> -        * PARs 5 through 8 are additional NS16550 UARTS
> -        * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
> -        */
> -       writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
> -       writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
> -       writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
> -       writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
> -
> -       /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
> -       writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
> -       writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
> -
> -       /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
> -       writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
> -
> -       /*
> -        * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
> -        * Already configured in board_init16 (eNET_start16.S)
> -        *
> -        * PAR 15 is Boot ROM
> -        * Already configured in board_init16 (eNET_start16.S)
> -        */
> -}
> -
> -
> -int board_early_init_r(void)
> -{
> -       /* CPU Speed to 100MHz */
> -       gd->cpu_clk = 100000000;
> -
> -       /* Crystal is 33.000MHz */
> -       gd->bus_clk = 33000000;
> -
> -       return 0;
> -}
> -
> -void show_boot_progress(int val)
> -{
> -       uchar led_mask;
> -
> -       led_mask = 0x00;
> -
> -       if (val < 0)
> -               led_mask |= LED_ERR_BITMASK;
> -
> -       led_mask |= (uchar)(val & 0x001f);
> -       outb(led_mask, LED_LATCH_ADDRESS);
> -}
> -
> -
> -int last_stage_init(void)
> -{
> -       outb(0x00, LED_LATCH_ADDRESS);
> -
> -       register_timer_isr(enet_timer_isr);
> -
> -       printf("Serck Controls eNET\n");
> -
> -       return 0;
> -}
> -
> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
> -{
> -       if (banknum == 0) {     /* non-CFI boot flash */
> -               info->portwidth = FLASH_CFI_8BIT;
> -               info->chipwidth = FLASH_CFI_BY8;
> -               info->interface = FLASH_CFI_X8;
> -               return 1;
> -       } else {
> -               return 0;
> -       }
> -}
> -
> -int board_eth_init(bd_t *bis)
> -{
> -       return pci_eth_init(bis);
> -}
> -
> -void setup_pcat_compatibility()
> -{
> -       /* disable global interrupt mode */
> -       writeb(0x40, &sc520_mmcr->picicr);
> -
> -       /* set all irqs to edge */
> -       writeb(0x00, &sc520_mmcr->pic_mode[0]);
> -       writeb(0x00, &sc520_mmcr->pic_mode[1]);
> -       writeb(0x00, &sc520_mmcr->pic_mode[2]);
> -
> -       /*
> -        *  active low polarity on PIC interrupt pins,
> -        *  active high polarity on all other irq pins
> -        */
> -       writew(0x0000, &sc520_mmcr->intpinpol);
> -
> -       /*
> -        * PIT 0 -> IRQ0
> -        * RTC -> IRQ8
> -        * FP error -> IRQ13
> -        * UART1 -> IRQ4
> -        * UART2 -> IRQ3
> -        */
> -       writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
> -       writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
> -       writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
> -       writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
> -       writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
> -
> -       /* Disable all other interrupt sources */
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
> -}
> -
> -void enet_timer_isr(void)
> -{
> -       static long enet_ticks;
> -
> -       enet_ticks++;
> -
> -       /* Toggle Watchdog every 100ms */
> -       if ((enet_ticks % 100) == 0)
> -               hw_watchdog_reset();
> -
> -       /* Toggle Run LED every 500ms */
> -       if ((enet_ticks % 500) == 0)
> -               enet_toggle_run_led();
> -}
> -
> -void hw_watchdog_reset(void)
> -{
> -       /* Watchdog Reset must be atomic */
> -       long flag = disable_interrupts();
> -
> -       if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
> -               sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
> -       else
> -               sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
> -
> -       if (flag)
> -               enable_interrupts();
> -}
> -
> -void enet_toggle_run_led(void)
> -{
> -       unsigned char leds_state = inb(LED_LATCH_ADDRESS);
> -       if (leds_state & LED_RUN_BITMASK)
> -               outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
> -       else
> -               outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
> -}
> diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
> deleted file mode 100644
> index 5af4ef7..0000000
> --- a/board/eNET/eNET_pci.c
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/*
> - * (C) Copyright 2008,2009
> - * Graeme Russ, <graeme.russ@gmail.com>
> - *
> - * (C) Copyright 2002
> - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <pci.h>
> -#include <asm/pci.h>
> -#include <asm/arch/pci.h>
> -
> -static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
> -{
> -       /* a configurable lists of IRQs to steal when we need one */
> -       static int irq_list[] = {
> -               CONFIG_SYS_FIRST_PCI_IRQ,
> -               CONFIG_SYS_SECOND_PCI_IRQ,
> -               CONFIG_SYS_THIRD_PCI_IRQ,
> -               CONFIG_SYS_FORTH_PCI_IRQ
> -       };
> -       static int next_irq_index;
> -
> -       uchar tmp_pin;
> -       int pin;
> -
> -       pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
> -       pin = tmp_pin;
> -
> -       pin -= 1; /* PCI config space use 1-based numbering */
> -       if (pin == -1)
> -               return; /* device use no irq */
> -
> -       /* map device number +  pin to a pin on the sc520 */
> -       switch (PCI_DEV(dev)) {
> -       case 12:        /* First Ethernet Chip */
> -               pin += SC520_PCI_INTA;
> -               break;
> -
> -       case 13:        /* Second Ethernet Chip */
> -               pin += SC520_PCI_INTB;
> -               break;
> -
> -       default:
> -               return;
> -       }
> -
> -       pin &= 3; /* wrap around */
> -
> -       if (sc520_pci_ints[pin] == -1) {
> -               /* re-route one interrupt for us */
> -               if (next_irq_index > 3)
> -                       return;
> -
> -               if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
> -                       return;
> -
> -               next_irq_index++;
> -       }
> -
> -       if (-1 != sc520_pci_ints[pin])
> -               pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
> -                                          sc520_pci_ints[pin]);
> -
> -       printf("fixup_irq: device %d pin %c irq %d\n",
> -              PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
> -}
> -
> -static struct pci_controller enet_hose = {
> -       fixup_irq: pci_enet_fixup_irq,
> -};
> -
> -void pci_init_board(void)
> -{
> -       pci_sc520_init(&enet_hose);
> -}
> -
> -int pci_set_regions(struct pci_controller *hose)
> -{
> -       /* System memory space */
> -       pci_set_region(hose->regions + 0,
> -                      SC520_PCI_MEMORY_BUS,
> -                      SC520_PCI_MEMORY_PHYS,
> -                      SC520_PCI_MEMORY_SIZE,
> -                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
> -
> -       /* ISA/PCI memory space */
> -       pci_set_region(hose->regions + 1,
> -                      SC520_ISA_MEM_BUS,
> -                      SC520_ISA_MEM_PHYS,
> -                      SC520_ISA_MEM_SIZE,
> -                      PCI_REGION_MEM);
> -
> -       /* PCI I/O space */
> -       pci_set_region(hose->regions + 2,
> -                      SC520_PCI_IO_BUS,
> -                      SC520_PCI_IO_PHYS,
> -                      SC520_PCI_IO_SIZE,
> -                      PCI_REGION_IO);
> -
> -       /* ISA/PCI I/O space */
> -       pci_set_region(hose->regions + 3,
> -                      SC520_ISA_IO_BUS,
> -                      SC520_ISA_IO_PHYS,
> -                      SC520_ISA_IO_SIZE,
> -                      PCI_REGION_IO);
> -
> -       return 4;
> -}
> diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
> deleted file mode 100644
> index 0dec7ea..0000000
> --- a/board/eNET/eNET_start.S
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Graeme Russ, graeme.russ@gmail.com.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include "hardware.h"
> -
> -/* board early intialization */
> -.globl early_board_init
> -early_board_init:
> -       /* No 32-bit board specific initialisation */
> -       jmp     early_board_init_ret
> diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
> deleted file mode 100644
> index 5e3f44c..0000000
> --- a/board/eNET/eNET_start16.S
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Graeme Russ, graeme.russ@gmail.com.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -/*
> - * 16bit initialization code.
> - * This code have to map the area of the boot flash
> - * that is used by U-boot to its final destination.
> - */
> -
> -#include "config.h"
> -#include "hardware.h"
> -#include <asm/arch/sc520.h>
> -#include <generated/asm-offsets.h>
> -
> -.text
> -.section .start16, "ax"
> -.code16
> -.globl board_init16
> -board_init16:
> -       /* Alias MMCR to 0xdf000 */
> -       movw    $0xfffc, %dx
> -       movl    $0x800df0cb, %eax
> -       outl    %eax, %dx
> -
> -       /* Set ds to point to MMCR alias */
> -       movw    $0xdf00, %ax
> -       movw    %ax, %ds
> -
> -       /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
> -       movl    $GENERATED_SC520_PAR14, %edi
> -       movl    $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
> -       movl    %eax, (%di)
> -
> -       /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
> -       movl    $GENERATED_SC520_PAR15, %edi
> -       movl    $CONFIG_SYS_SC520_LLIO_PAR, %eax
> -       movl    %eax, (%di)
> -
> -       /* Disabe MMCR alias */
> -       movw    $0xfffc, %dx
> -       movl    $0x000000cb, %eax
> -       outl    %eax, %dx
> -
> -       jmp     board_init16_ret
> -
> -.section .bios, "ax"
> -.code16
> -.globl realmode_reset
> -.hidden realmode_reset
> -.type realmode_reset, @function
> -realmode_reset:
> -       /* Alias MMCR to 0xdf000 */
> -       movw    $0xfffc, %dx
> -       movl    $0x800df0cb, %eax
> -       outl    %eax, %dx
> -
> -       /* Set ds to point to MMCR alias */
> -       movw    $0xdf00, %ax
> -       movw    %ax, %ds
> -
> -       /* issue software reset thorugh MMCR */
> -       movl    $0xd72, %edi
> -       movb    $0x01, %al
> -       movb    %al, (%di)
> -
> -1:     hlt
> -       jmp     1
> diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
> deleted file mode 100644
> index dec2cd8..0000000
> --- a/board/eNET/hardware.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Graeme Russ, graeme.russ@gmail.com.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#ifndef HARDWARE_H_
> -#define HARDWARE_H_
> -
> -#define LED_LATCH_ADDRESS      0x1002
> -#define LED_RUN_BITMASK                0x01
> -#define LED_1_BITMASK          0x02
> -#define LED_2_BITMASK          0x04
> -#define LED_RX_BITMASK         0x08
> -#define LED_TX_BITMASK         0x10
> -#define LED_ERR_BITMASK                0x20
> -#define WATCHDOG_PIO_BIT       0x8000
> -
> -#endif /* HARDWARE_H_ */
> diff --git a/boards.cfg b/boards.cfg
> index cd220af..b1319aa 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -1123,7 +1123,5 @@ gr_ep2s60                    sparc       leon3
> -                   gaisler
>  grsim                        sparc       leon3       -
> gaisler
>  gr_xc3s_1500                 sparc       leon3       -
> gaisler
>  coreboot-x86                 x86         x86        coreboot
>  chromebook-x86 coreboot    coreboot:SYS_TEXT_BASE=0x01110000
> -eNET                         x86         x86        eNET                -
>              sc520       eNET:SYS_TEXT_BASE=0x38040000
> -eNET_SRAM                    x86         x86        eNET                -
>              sc520       eNET:SYS_TEXT_BASE=0x19000000
>  # Target                     ARCH        CPU         Board name
>  Vendor                SoC         Options
>
>  ########################################################################################################################
> diff --git a/include/configs/eNET.h b/include/configs/eNET.h
> deleted file mode 100644
> index 28cf95b..0000000
> --- a/include/configs/eNET.h
> +++ /dev/null
> @@ -1,619 +0,0 @@
> -/*
> - * (C) Copyright 2008
> - * Graeme Russ, graeme.russ@gmail.com.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <asm/ibmpc.h>
> -/*
> - * board/config.h - configuration options, board specific
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - * (easy to change)
> - */
> -#define CONFIG_SYS_SC520
> -#define CONFIG_SYS_SC520_SSI
> -#define CONFIG_SHOW_BOOT_PROGRESS
> -#define CONFIG_LAST_STAGE_INIT
> -
> -/*-----------------------------------------------------------------------
> - * Watchdog Configuration
> - * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
> - * bottom (processor) board MUST be removed!
> - */
> -#undef CONFIG_WATCHDOG
> -#define CONFIG_HW_WATCHDOG
> -
> -/*-----------------------------------------------------------------------
> - * Real Time Clock Configuration
> - */
> -#define CONFIG_RTC_MC146818
> -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS         0
> -
> -/*-----------------------------------------------------------------------
> - * Serial Configuration
> - */
> -#define CONFIG_CONS_INDEX                      1
> -#define CONFIG_SYS_NS16550
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE            1
> -#define CONFIG_SYS_NS16550_CLK                 1843200
> -#define CONFIG_BAUDRATE                                9600
> -#define CONFIG_SYS_BAUDRATE_TABLE              {300, 600, 1200, 2400,
> 4800, \
> -                                                9600, 19200, 38400,
> 115200}
> -#define CONFIG_SYS_NS16550_COM1                        UART0_BASE
> -#define CONFIG_SYS_NS16550_COM2                        UART1_BASE
> -#define CONFIG_SYS_NS16550_COM3                        (0x1000 +
> UART0_BASE)
> -#define CONFIG_SYS_NS16550_COM4                        (0x1000 +
> UART1_BASE)
> -#define CONFIG_SYS_NS16550_PORT_MAPPED
> -
> -/*-----------------------------------------------------------------------
> - * Video Configuration
> - */
> -#undef CONFIG_VIDEO
> -#undef CONFIG_CFB_CONSOLE
> -
> -/*-----------------------------------------------------------------------
> - * Command line configuration.
> - */
> -#include <config_cmd_default.h>
> -
> -#define CONFIG_CMD_BDI
> -#define CONFIG_CMD_BOOTD
> -#define CONFIG_CMD_CONSOLE
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_ECHO
> -#define CONFIG_CMD_FLASH
> -#define CONFIG_CMD_FPGA
> -#define CONFIG_CMD_IMI
> -#define CONFIG_CMD_IMLS
> -#define CONFIG_CMD_IRQ
> -#define CONFIG_CMD_ITEST
> -#define CONFIG_CMD_LOADB
> -#define CONFIG_CMD_LOADS
> -#define CONFIG_CMD_MEMORY
> -#define CONFIG_CMD_MISC
> -#define CONFIG_CMD_NET
> -#undef CONFIG_CMD_NFS
> -#define CONFIG_CMD_PCI
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_RUN
> -#define CONFIG_CMD_SAVEENV
> -#define CONFIG_CMD_SETGETDCR
> -#define CONFIG_CMD_SOURCE
> -#define CONFIG_CMD_XIMG
> -#define CONFIG_CMD_ZBOOT
> -
> -#define CONFIG_BOOTDELAY                       15
> -#define CONFIG_BOOTARGS
>  "root=/dev/mtdblock0 console=ttyS0,9600"
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE                   115200
> -#define CONFIG_KGDB_SER_INDEX                  2
> -#endif
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define        CONFIG_SYS_LONGHELP
> -#define        CONFIG_SYS_PROMPT                       "boot > "
> -#define        CONFIG_SYS_CBSIZE                       256
> -#define        CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE
> + \
> -                                                sizeof(CONFIG_SYS_PROMPT)
> + \
> -                                                16)
> -#define        CONFIG_SYS_MAXARGS                      16
> -#define CONFIG_SYS_BARGSIZE                    CONFIG_SYS_CBSIZE
> -
> -#define CONFIG_SYS_MEMTEST_START               0x00100000
> -#define CONFIG_SYS_MEMTEST_END                 0x01000000
> -#define        CONFIG_SYS_LOAD_ADDR                    0x100000
> -#define        CONFIG_SYS_HZ                           1000
> -
> -/*-----------------------------------------------------------------------
> - * SDRAM Configuration
> - */
> -#define CONFIG_SYS_SDRAM_DRCTMCTL              0x18
> -#define CONFIG_SYS_SDRAM_REFRESH_RATE          156
> -#define CONFIG_NR_DRAM_BANKS                   4
> -
> -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
> -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
> -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
> -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
> -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
> -
> -/*-----------------------------------------------------------------------
> - * CPU Features
> - */
> -#define CONFIG_SYS_SC520_HIGH_SPEED            0
> -#define CONFIG_SYS_SC520_RESET
> -#define CONFIG_SYS_SC520_TIMER
> -#undef  CONFIG_SYS_GENERIC_TIMER
> -#define CONFIG_SYS_PCAT_INTERRUPTS
> -#define CONFIG_SYS_NUM_IRQS                    16
> -#define CONFIG_SYS_PC_BIOS
> -#define CONFIG_SYS_PCI_BIOS
> -#define CONFIG_SYS_X86_REALMODE
> -#define CONFIG_SYS_X86_ISR_TIMER
> -
> -/*-----------------------------------------------------------------------
> - * Memory organization:
> - * 32kB Stack
> - * 16kB Cache-As-RAM @ 0x19200000
> - * 256kB Monitor
> - * (128kB + Environment Sector Size) malloc pool
> - */
> -#define CONFIG_SYS_STACK_SIZE                  (32 * 1024)
> -#define CONFIG_SYS_CAR_ADDR                    0x19200000
> -#define CONFIG_SYS_CAR_SIZE                    (16 * 1024)
> -#define CONFIG_SYS_MONITOR_BASE
>  CONFIG_SYS_TEXT_BASE
> -#define CONFIG_SYS_MONITOR_LEN                 (256 * 1024)
> -#define CONFIG_SYS_MALLOC_LEN                  (CONFIG_ENV_SECT_SIZE + \
> -                                                128*1024)
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -/*-----------------------------------------------------------------------
> - * FLASH configuration
> - * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
> - * 16MB StrataFlash #1 @ 0x10000000
> - * 16MB StrataFlash #2 @ 0x11000000
> - */
> -#define CONFIG_FLASH_CFI_DRIVER
> -#define CONFIG_FLASH_CFI_LEGACY
> -#define CONFIG_SYS_FLASH_CFI
> -#define CONFIG_SYS_MAX_FLASH_BANKS             3
> -#define CONFIG_SYS_FLASH_BASE                  0x38000000
> -#define CONFIG_SYS_FLASH_BASE_1                        0x10000000
> -#define CONFIG_SYS_FLASH_BASE_2                        0x11000000
> -#define CONFIG_SYS_FLASH_BANKS_LIST            {CONFIG_SYS_FLASH_BASE,   \
> -                                                CONFIG_SYS_FLASH_BASE_1, \
> -                                                CONFIG_SYS_FLASH_BASE_2}
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> -#define CONFIG_SYS_MAX_FLASH_SECT              128
> -#define CONFIG_SYS_FLASH_CFI_WIDTH             FLASH_CFI_8BIT
> -#define CONFIG_SYS_FLASH_LEGACY_512Kx8
> -#define CONFIG_SYS_FLASH_ERASE_TOUT            2000    /* ms */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT            2000    /* ms */
> -
> -/*-----------------------------------------------------------------------
> - * Environment configuration
> - * - Boot flash is 512kB with 64kB sectors
> - * - StrataFlash is 32MB with 128kB sectors
> - * - Redundant embedded environment is 25% of the Boot flash
> - * - Redundant StrataFlash environment is <1% of the StrataFlash
> - * - Environment is therefore located in StrataFlash
> - * - Primary copy is located in first sector of first flash
> - * - Redundant copy is located in second sector of first flash
> - * - Stack is only 32kB, so environment size is limited to 4kB
> - */
> -#define CONFIG_ENV_IS_IN_FLASH
> -#define CONFIG_ENV_SECT_SIZE                   0x20000
> -#define CONFIG_ENV_SIZE                                0x01000
> -#define CONFIG_ENV_ADDR
>  CONFIG_SYS_FLASH_BASE_1
> -#define CONFIG_ENV_ADDR_REDUND                 (CONFIG_SYS_FLASH_BASE_1 +
> \
> -                                                CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE_REDUND                 CONFIG_ENV_SIZE
> -
> -/*-----------------------------------------------------------------------
> - * PCI configuration
> - */
> -#define CONFIG_PCI
> -#define CONFIG_PCI_PNP
> -#define CONFIG_SYS_FIRST_PCI_IRQ               10
> -#define CONFIG_SYS_SECOND_PCI_IRQ              9
> -#define CONFIG_SYS_THIRD_PCI_IRQ               11
> -#define CONFIG_SYS_FORTH_PCI_IRQ               15
> -
> -/*-----------------------------------------------------------------------
> - * Network device (TRL8100B) support
> - */
> -#define CONFIG_RTL8139
> -
> -/*-----------------------------------------------------------------------
> - * BOOTCS Control (for AM29LV040B-120JC)
> - *
> - * 000 0 00 0 000 11 0 011 }- 0x0033
> - * \ / | \| | \ / \| | \ /
> - *  |  |  | |  |   | |  |
> - *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
> - *  |  |  | |  |   | +------- Reserved
> - *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
> - *  |  |  | |  +------------- Reserved
> - *  |  |  | +---------------- Non-Paged Mode
> - *  |  |  +------------------ 8 Bit Wide
> - *  |  +--------------------- GP Bus
> - *  +------------------------ Reserved
> - */
> -#define CONFIG_SYS_SC520_BOOTCS_CTRL           0x0033
> -
> -/*-----------------------------------------------------------------------
> - * ROMCS Control (for E28F128J3A-150 StrataFlash)
> - *
> - * 000 0 01 1 000 01 0 101 }- 0x0615
> - * \ / | \| | \ / \| | \ /
> - *  |  |  | |  |   | |  |
> - *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
> - *  |  |  | |  |   | +------- Reserved
> - *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
> - *  |  |  | |  +------------- Reserved
> - *  |  |  | +---------------- Paged Mode
> - *  |  |  +------------------ 16 Bit Wide
> - *  |  +--------------------- GP Bus
> - *  +------------------------ Reserved
> - */
> -#define CONFIG_SYS_SC520_ROMCS1_CTRL           0x0615
> -#define CONFIG_SYS_SC520_ROMCS2_CTRL           0x0615
> -
> -/*-----------------------------------------------------------------------
> - * SC520 General Purpose Bus configuration
> - *
> - * Chip Select Offset          1 Clock Cycle
> - * Chip Select Pulse Width     8 Clock Cycles
> - * Chip Select Read Offset     2 Clock Cycles
> - * Chip Select Read Width      6 Clock Cycles
> - * Chip Select Write Offset    2 Clock Cycles
> - * Chip Select Write Width     6 Clock Cycles
> - * Chip Select Recovery Time   2 Clock Cycles
> - *
> - * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
> - *
> - *   |<-------------General Purpose Bus Cycle---------------->|
> - *   |                                                        |
> - * ----------------------\__________________/------------------
> - *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
> - *
> - * ------------------------\_______________/-------------------
> - *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
> - *
> - * --------------------------\_______________/-----------------
> - *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
> - *
> - * ________/-----------\_______________________________________
> - *   |<--->|<--------->|
> - *      ^         ^
> - * (GPALEOFF + 1) |
> - *                |
> - *         (GPALEW + 1)
> - */
> -#define CONFIG_SYS_SC520_GPCSOFF               0x00
> -#define CONFIG_SYS_SC520_GPCSPW                        0x07
> -#define CONFIG_SYS_SC520_GPRDOFF               0x01
> -#define CONFIG_SYS_SC520_GPRDW                 0x05
> -#define CONFIG_SYS_SC520_GPWROFF               0x01
> -#define CONFIG_SYS_SC520_GPWRW                 0x05
> -#define CONFIG_SYS_SC520_GPCSRT                        0x01
> -
> -/*-----------------------------------------------------------------------
> - * SC520 Programmable I/O configuration
> - *
> - * Pin   Mode          Dir.    Description
> - * ----------------------------------------------------------------------
> - * PIO0   PIO          Output  Unused
> - * PIO1   GPBHE#       Output  GP Bus Byte High Enable (active low)
> - * PIO2   PIO          Output  Auxiliary power output enable
> - * PIO3   GPAEN                Output  GP Bus Address Enable
> - * PIO4   PIO          Output  Top Board Enable (active low)
> - * PIO5   PIO          Output  StrataFlash 16 bit mode (low = 8 bit mode)
> - * PIO6   PIO          Input   Data output of Power Supply ADC
> - * PIO7   PIO          Output  Clock input to Power Supply ADC
> - * PIO8   PIO          Output  Chip Select input of Power Supply ADC
> - * PIO9   PIO          Output  StrataFlash 1 Reset / Power Down (active
> low)
> - * PIO10  PIO          Output  StrataFlash 2 Reset / Power Down (active
> low)
> - * PIO11  PIO          Input   StrataFlash 1 Status
> - * PIO12  PIO          Input   StrataFlash 2 Status
> - * PIO13  GPIRQ10#     Input   Can Bus / I2C IRQ (active low)
> - * PIO14  PIO          Input   Low Input Voltage Warning (active low)
> - * PIO15  PIO          Output  Watchdog (must toggle at least every 1.6s)
> - * PIO16  PIO          Input   Power Fail
> - * PIO17  GPIRQ6       Input   Compact Flash 1 IRQ (active low)
> - * PIO18  GPIRQ5       Input   Compact Flash 2 IRQ (active low)
> - * PIO19  GPIRQ4#      Input   Dual-Port RAM IRQ (active low)
> - * PIO20  GPIRQ3       Input   UART D IRQ
> - * PIO21  GPIRQ2       Input   UART C IRQ
> - * PIO22  GPIRQ1       Input   UART B IRQ
> - * PIO23  GPIRQ0       Input   UART A IRQ
> - * PIO24  GPDBUFOE#    Output  GP Bus Data Bus Buffer Output Enable
> - * PIO25  PIO          Input   Battery OK Indication
> - * PIO26  GPMEMCS16#   Input   GP Bus Memory Chip-Select 16-bit access
> - * PIO27  GPCS0#       Output  SRAM 1 Chip Select
> - * PIO28  PIO          Input   Top Board UART CTS
> - * PIO29  PIO          Output  FPGA Program Mode (active low)
> - * PIO30  PIO          Input   FPGA Initialised (active low)
> - * PIO31  PIO          Input   FPGA Done (active low)
> - */
> -#define CONFIG_SYS_SC520_PIOPFS15_0            0x200a
> -#define CONFIG_SYS_SC520_PIOPFS31_16           0x0dfe
> -#define CONFIG_SYS_SC520_PIODIR15_0            0x87bf
> -#define CONFIG_SYS_SC520_PIODIR31_16           0x2900
> -
> -/*-----------------------------------------------------------------------
> - * PIO Pin defines
> - */
> -#define CONFIG_SYS_ENET_AUX_PWR                        0x0004
> -#define CONFIG_SYS_ENET_TOP_BRD_PWR            0x0010
> -#define CONFIG_SYS_ENET_SF_WIDTH               0x0020
> -#define CONFIG_SYS_ENET_PWR_ADC_DATA           0x0040
> -#define CONFIG_SYS_ENET_PWR_ADC_CLK            0x0080
> -#define CONFIG_SYS_ENET_PWR_ADC_CS             0x0100
> -#define CONFIG_SYS_ENET_SF1_MODE               0x0200
> -#define CONFIG_SYS_ENET_SF2_MODE               0x0400
> -#define CONFIG_SYS_ENET_SF1_STATUS             0x0800
> -#define CONFIG_SYS_ENET_SF2_STATUS             0x1000
> -#define CONFIG_SYS_ENET_PWR_STATUS             0x4000
> -#define CONFIG_SYS_ENET_WATCHDOG               0x8000
> -
> -#define CONFIG_SYS_ENET_PWR_FAIL               0x0001
> -#define CONFIG_SYS_ENET_BAT_OK                 0x0200
> -#define CONFIG_SYS_ENET_TOP_BRD_CTS            0x1000
> -#define CONFIG_SYS_ENET_FPGA_PROG              0x2000
> -#define CONFIG_SYS_ENET_FPGA_INIT              0x4000
> -#define CONFIG_SYS_ENET_FPGA_DONE              0x8000
> -
> -/*-----------------------------------------------------------------------
> - * Chip Select Pin Function Select
> - *
> - * 1 1 1 1 1 0 0 0 }- 0xf8
> - * | | | | | | | |
> - * | | | | | | | +--- Reserved
> - * | | | | | | +----- GPCS1_SEL = ROMCS1#
> - * | | | | | +------- GPCS2_SEL = ROMCS2#
> - * | | | | +--------- GPCS3_SEL = GPCS3
> - * | | | +----------- GPCS4_SEL = GPCS4
> - * | | +------------- GPCS5_SEL = GPCS5
> - * | +--------------- GPCS6_SEL = GPCS6
> - * +----------------- GPCS7_SEL = GPCS7
> - */
> -#define CONFIG_SYS_SC520_CSPFS                 0xf8
> -
> -/*-----------------------------------------------------------------------
> - * Clock Select (CLKTIMER[CLKTEST] pin)
> - *
> - * 0 111 00 1 0 }- 0x72
> - * | \ / \| | |
> - * |  |   | | +--- Pin Disabled
> - * |  |   | +----- Pin is an output
> - * |  |   +------- Reserved
> - * |  +----------- Disabled (pin stays Low)
> - * +-------------- Reserved
> - */
> -#define CONFIG_SYS_SC520_CLKSEL                        0x72
> -
> -/*-----------------------------------------------------------------------
> - * Address Decode Control
> - *
> - * 0 00 0 0 0 0 0 }- 0x00
> - * | \| | | | | |
> - * |  | | | | | +--- Integrated UART 1 is enabled
> - * |  | | | | +----- Integrated UART 2 is enabled
> - * |  | | | +------- Integrated RTC is enabled
> - * |  | | +--------- Reserved
> - * |  | +----------- I/O Hole accesses are forwarded to the external GP
> bus
> - * |  +------------- Reserved
> - * +---------------- Write-protect violations do not generate an IRQ
> - */
> -#define CONFIG_SYS_SC520_ADDDECCTL             0x00
> -
> -/*-----------------------------------------------------------------------
> - * UART Control
> - *
> - * 00000 1 1 1 }- 0x07
> - * \___/ | | |
> - *   |   | | +--- Transmit TC interrupt enable
> - *   |   | +----- Receive TC interrupt enable
> - *   |   +------- 1.8432 MHz
> - *   +----------- Reserved
> - */
> -#define CONFIG_SYS_SC520_UART1CTL              0x07
> -#define CONFIG_SYS_SC520_UART2CTL              0x07
> -
> -/*-----------------------------------------------------------------------
> - * System Arbiter Control
> - *
> - * 00000 1 1 0 }- 0x06
> - * \___/ | | |
> - *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
> - *   |   | +----- The system arbiter operates in concurrent mode
> - *   |   +------- Park the PCI bus on the last master that acquired the
> bus
> - *   +----------- Reserved
> - */
> -#define CONFIG_SYS_SC520_SYSARBCTL             0x06
> -
> -/*-----------------------------------------------------------------------
> - * System Arbiter Master Enable
> - *
> - * 00000000000 0 0 0 1 1 }- 0x06
> - * \_________/ | | | | |
> - *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
> - *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
> - *      |      | | +------- PCI master REQ2 disabled
> - *      |      | +--------- PCI master REQ3 disabled
> - *      |      +----------- PCI master REQ4 disabled
> - *      +------------------ Reserved
> - */
> -#define CONFIG_SYS_SC520_SYSARBMENB            0x0003
> -
> -/*-----------------------------------------------------------------------
> - * System Arbiter Master Enable
> - *
> - * 0 0000 0 00 0000 1 000 }- 0x06
> - * | \__/ | \| \__/ | \_/
> - * |   |  |  |   |  |  +---- Reserved
> - * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
> - * |   |  |  |   +---------- Reserved
> - * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
> - * |   |  |                  retried
> - * |   |  +----------------- Target read FIFOs are not snooped during
> write
> - * |   |                     transactions
> - * |   +-------------------- Reserved
> - * +------------------------ Deassert the PCI bus reset signal
> - */
> -#define CONFIG_SYS_SC520_HBCTL                 0x08
> -
> -/*-----------------------------------------------------------------------
> - * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
> - * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
> - * \ / | | | | \----+----/ \-----+------/
> - *  |  | | | |      |            +---------- Start at 0x38000000
> - *  |  | | | |      +----------------------- 512kB Region Size
> - *  |  | | | |                               ((7 + 1) * 64kB)
> - *  |  | | | +------------------------------ 64kB Page Size
> - *  |  | | +-------------------------------- Writes Enabled (So it can be
> - *  |  | |                                   reprogrammed!)
> - *  |  | +---------------------------------- Caching Disabled
> - *  |  +------------------------------------ Execution Enabled
> - *  +--------------------------------------- BOOTCS
> - */
> -#define CONFIG_SYS_SC520_BOOTCS_PAR            0x8a01f800
> -
> -/*-----------------------------------------------------------------------
> - * Cache-As-RAM (Targets Boot Flash)
> - *
> - * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
> - * \ / | | | | \--+--/ \-------+--------/
> - *  |  | | | |    |            +------------ Start at 0x19200000
> - *  |  | | | |    +------------------------- 64k Region Size
> - *  |  | | | |                               ((15 + 1) * 4kB)
> - *  |  | | | +------------------------------ 4kB Page Size
> - *  |  | | +-------------------------------- Writes Enabled
> - *  |  | +---------------------------------- Caching Enabled
> - *  |  +------------------------------------ Execution Prevented
> - *  +--------------------------------------- BOOTCS
> - */
> -#define CONFIG_SYS_SC520_CAR_PAR               0x903d9200
> -
> -/*-----------------------------------------------------------------------
> - * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000,
> GPCS6
> - *
> - * 001 110 0 000100000 0001000000000000 }- 0x38201000
> - * \ / \ / | \---+---/ \------+-------/
> - *  |   |  |     |            +----------- Start at 0x00001000
> - *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
> - *  |   |  +------------------------------ Ignored
> - *  |   +--------------------------------- GPCS6
> - *  +------------------------------------- GP Bus I/O
> - */
> -#define CONFIG_SYS_SC520_LLIO_PAR              0x38201000
> -
> -/*-----------------------------------------------------------------------
> - * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
> - * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
> - *
> - * 010 101 0 0000000 100000000000000000 }- 0x54020000
> - * 010 111 0 0000000 100000000000000001 }- 0x5c020001
> - * \ / \ / | \--+--/ \-------+--------/
> - *  |   |  |    |            +------------ Start at 0x200000000
> - *  |   |  |    |                                   0x200010000
> - *  |   |  |    +------------------------- 4kB Region Size
> - *  |   |  |                               ((0 + 1) * 4kB)
> - *  |   |  +------------------------------ 4k Page Size
> - *  |   +--------------------------------- GPCS5
> - *  |                                      GPCS7
> - *  +------------------------------------- GP Bus Memory
> - */
> -#define CONFIG_SYS_SC520_CF1_PAR               0x54020000
> -#define CONFIG_SYS_SC520_CF2_PAR               0x5c020001
> -
> -/*-----------------------------------------------------------------------
> - * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
> - * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
> - * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
> - * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
> - *
> - * 001 000 0 000000111 0001001111111000 }- 0x200713f8
> - * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
> - * 001 011 0 000000111 0001001011111000 }- 0x300711f8
> - * 001 011 0 000000111 0001001011111000 }- 0x340710f8
> - * \ / \ / | \---+---/ \------+-------/
> - *  |   |  |     |            +----------- Start at 0x013f8
> - *  |   |  |     |                                  0x012f8
> - *  |   |  |     |                                  0x011f8
> - *  |   |  |     |                                  0x010f8
> - *  |   |  |     +------------------------ 33 Bytes (32 + 1)
> - *  |   |  +------------------------------ Ignored
> - *  |   +--------------------------------- GPCS6
> - *  +------------------------------------- GP Bus I/O
> - */
> -#define CONFIG_SYS_SC520_UARTA_PAR             0x200713f8
> -#define CONFIG_SYS_SC520_UARTB_PAR             0x2c0712f8
> -#define CONFIG_SYS_SC520_UARTC_PAR             0x300711f8
> -#define CONFIG_SYS_SC520_UARTD_PAR             0x340710f8
> -
> -/*-----------------------------------------------------------------------
> - * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
> - * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
> - *
> - * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
> - * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
> - * \ / | | | | \----+----/ \-----+------/
> - *  |  | | | |      |            +---------- Start at 0x10000000
> - *  |  | | | |      |                                 0x11000000
> - *  |  | | | |      +----------------------- 16MB Region Size
> - *  |  | | | |                               ((255 + 1) * 64kB)
> - *  |  | | | +------------------------------ 64kB Page Size
> - *  |  | | +-------------------------------- Writes Enabled
> - *  |  | +---------------------------------- Caching Disabled
> - *  |  +------------------------------------ Execution Enabled
> - *  +--------------------------------------- ROMCS1
> - *                                           ROMCS2
> - */
> -#define CONFIG_SYS_SC520_SF1_PAR               0xaa3fd000
> -#define CONFIG_SYS_SC520_SF2_PAR               0xca3fd100
> -
> -/*-----------------------------------------------------------------------
> - * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
> - * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
> - *
> - * 010 000 1 00000001111 01100100000000 }- 0x4203d900
> - * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
> - * \ / \ / | \----+----/ \-----+------/
> - *  |   |  |      |            +---------- Start at 0x19000000
> - *  |   |  |      |                                 0x19100000
> - *  |   |  |      +----------------------- 1MB Region Size
> - *  |   |  |                               ((15 + 1) * 64kB)
> - *  |   |  +------------------------------ 64kB Page Size
> - *  |   +--------------------------------- GPCS0
> - *  |                                      GPCS3
> - *  +------------------------------------- GP Bus Memory
> - */
> -#define CONFIG_SYS_SC520_SRAM1_PAR             0x4203d900
> -#define CONFIG_SYS_SC520_SRAM2_PAR             0x4e03d910
> -
> -/*-----------------------------------------------------------------------
> - * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
> - *
> - * 010 100 0 00000000 11000000100000000 }- 0x50018100
> - * \ / \ / | \---+--/ \-------+-------/
> - *  |   |  |     |            +----------- Start at 0x18100000
> - *  |   |  |     +------------------------ 4kB Region Size
> - *  |   |  |                               ((0 + 1) * 4kB)
> - *  |   |  +------------------------------ 4kB Page Size
> - *  |   +--------------------------------- GPCS4
> - *  +------------------------------------- GP Bus Memory
> - */
> -#define CONFIG_SYS_SC520_DPRAM_PAR             0x50018100
> -
> -#endif /* __CONFIG_H */
> --
> 1.8.1
>
>
Simon Glass - Feb. 15, 2013, 4:35 a.m.
On Thu, Feb 14, 2013 at 3:58 PM, Gabe Black <gabeblack@google.com> wrote:
> Acked-by: Gabe Black <gabeblack@chromium.org>
>
>
> On Thu, Feb 14, 2013 at 6:18 AM, Simon Glass <sjg@chromium.org> wrote:
>>
>> These are no longer used and should be removed.
>>
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> Acked-by: Graeme Russ <graeme.russ@gmail.com>

Applied to x86/master.

>> ---
>> Changes in v2: None
>>
>>  board/eNET/Makefile       |  52 ----
>>  board/eNET/eNET.c         | 284 ---------------------
>>  board/eNET/eNET_pci.c     | 128 ----------
>>  board/eNET/eNET_start.S   |  30 ---
>>  board/eNET/eNET_start16.S |  87 -------
>>  board/eNET/hardware.h     |  36 ---
>>  boards.cfg                |   2 -
>>  include/configs/eNET.h    | 619
>> ----------------------------------------------
>>  8 files changed, 1238 deletions(-)
>>  delete mode 100644 board/eNET/Makefile
>>  delete mode 100644 board/eNET/eNET.c
>>  delete mode 100644 board/eNET/eNET_pci.c
>>  delete mode 100644 board/eNET/eNET_start.S
>>  delete mode 100644 board/eNET/eNET_start16.S
>>  delete mode 100644 board/eNET/hardware.h
>>  delete mode 100644 include/configs/eNET.h
>>
>> diff --git a/board/eNET/Makefile b/board/eNET/Makefile
>> deleted file mode 100644
>> index ad1c5b1..0000000
>> --- a/board/eNET/Makefile
>> +++ /dev/null
>> @@ -1,52 +0,0 @@
>> -#
>> -# (C) Copyright 2008
>> -# Graeme Russ, graeme.russ@gmail.com.
>> -#
>> -# (C) Copyright 2006
>> -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
>> -#
>> -# (C) Copyright 2002
>> -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
>> -#
>> -# See file CREDITS for list of people who contributed to this
>> -# project.
>> -#
>> -# This program is free software; you can redistribute it and/or
>> -# modify it under the terms of the GNU General Public License as
>> -# published by the Free Software Foundation; either version 2 of
>> -# the License, or (at your option) any later version.
>> -#
>> -# This program is distributed in the hope that it will be useful,
>> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
>> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> -# GNU General Public License for more details.
>> -#
>> -# You should have received a copy of the GNU General Public License
>> -# along with this program; if not, write to the Free Software
>> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> -# MA 02111-1307 USA
>> -#
>> -
>> -include $(TOPDIR)/config.mk
>> -
>> -LIB    = $(obj)lib$(BOARD).o
>> -
>> -COBJS-y        += eNET.o
>> -COBJS-$(CONFIG_PCI) += eNET_pci.o
>> -SOBJS-y        += eNET_start16.o
>> -SOBJS-y        += eNET_start.o
>> -
>> -SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
>> -OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
>> -
>> -$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
>> -       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
>> -
>> -#########################################################################
>> -
>> -# defines $(obj).depend target
>> -include $(SRCTREE)/rules.mk
>> -
>> -sinclude $(obj).depend
>> -
>> -#########################################################################
>> diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
>> deleted file mode 100644
>> index 2f26470..0000000
>> --- a/board/eNET/eNET.c
>> +++ /dev/null
>> @@ -1,284 +0,0 @@
>> -/*
>> - * (C) Copyright 2008
>> - * Graeme Russ, graeme.russ@gmail.com.
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -#include <common.h>
>> -#include <asm/io.h>
>> -#include <asm/arch/sc520.h>
>> -#include <net.h>
>> -#include <netdev.h>
>> -
>> -#ifdef CONFIG_HW_WATCHDOG
>> -#include <watchdog.h>
>> -#endif
>> -
>> -#include "hardware.h"
>> -
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
>> -
>> -static void enet_timer_isr(void);
>> -static void enet_toggle_run_led(void);
>> -static void enet_setup_pars(void);
>> -
>> -/*
>> - * Miscellaneous platform dependent initializations
>> - */
>> -int board_early_init_f(void)
>> -{
>> -       u16 pio_out_cfg = 0x0000;
>> -
>> -       /* Configure General Purpose Bus timing */
>> -       writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
>> -       writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
>> -       writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
>> -       writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
>> -       writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
>> -       writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
>> -       writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
>> -
>> -       /* Configure Programmable Input/Output Pins */
>> -       writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
>> -       writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
>> -       writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
>> -       writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
>> -       writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
>> -       writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
>> -
>> -       /*
>> -        * Turn off top board
>> -        * Set StrataFlash chips to 16-bit width
>> -        * Set StrataFlash chips to normal (non reset/power down) mode
>> -        */
>> -       pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
>> -       pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
>> -       pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
>> -       pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
>> -       writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
>> -
>> -       /* Turn off auxiliary power output */
>> -       writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
>> -
>> -       /* Clear FPGA program mode */
>> -       writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
>> -
>> -       enet_setup_pars();
>> -
>> -       /* Disable Watchdog */
>> -       writew(0x3333, &sc520_mmcr->wdtmrctl);
>> -       writew(0xcccc, &sc520_mmcr->wdtmrctl);
>> -       writew(0x0000, &sc520_mmcr->wdtmrctl);
>> -
>> -       /* Chip Select Configuration */
>> -       writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
>> -       writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
>> -       writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
>> -
>> -       writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
>> -       writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
>> -       writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
>> -
>> -       writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
>> -       writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
>> -
>> -       /* enable posted-writes */
>> -       writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
>> -
>> -       return 0;
>> -}
>> -
>> -static void enet_setup_pars(void)
>> -{
>> -       /*
>> -        * PARs 11 and 12 are 2MB SRAM @ 0x19000000
>> -        *
>> -        * These are setup now because older version of U-Boot have them
>> -        * mapped to a different PAR which gets clobbered which prevents
>> -        * using SRAM for warm-booting a new image
>> -        */
>> -       writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
>> -       writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
>> -
>> -       /* PARs 0 and 1 are Compact Flash slots (4kB each) */
>> -       writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
>> -       writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
>> -
>> -       /* PAR 2 is used for Cache-As-RAM */
>> -
>> -       /*
>> -        * PARs 5 through 8 are additional NS16550 UARTS
>> -        * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
>> -        */
>> -       writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
>> -       writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
>> -       writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
>> -       writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
>> -
>> -       /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
>> -       writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
>> -       writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
>> -
>> -       /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
>> -       writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
>> -
>> -       /*
>> -        * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
>> -        * Already configured in board_init16 (eNET_start16.S)
>> -        *
>> -        * PAR 15 is Boot ROM
>> -        * Already configured in board_init16 (eNET_start16.S)
>> -        */
>> -}
>> -
>> -
>> -int board_early_init_r(void)
>> -{
>> -       /* CPU Speed to 100MHz */
>> -       gd->cpu_clk = 100000000;
>> -
>> -       /* Crystal is 33.000MHz */
>> -       gd->bus_clk = 33000000;
>> -
>> -       return 0;
>> -}
>> -
>> -void show_boot_progress(int val)
>> -{
>> -       uchar led_mask;
>> -
>> -       led_mask = 0x00;
>> -
>> -       if (val < 0)
>> -               led_mask |= LED_ERR_BITMASK;
>> -
>> -       led_mask |= (uchar)(val & 0x001f);
>> -       outb(led_mask, LED_LATCH_ADDRESS);
>> -}
>> -
>> -
>> -int last_stage_init(void)
>> -{
>> -       outb(0x00, LED_LATCH_ADDRESS);
>> -
>> -       register_timer_isr(enet_timer_isr);
>> -
>> -       printf("Serck Controls eNET\n");
>> -
>> -       return 0;
>> -}
>> -
>> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
>> -{
>> -       if (banknum == 0) {     /* non-CFI boot flash */
>> -               info->portwidth = FLASH_CFI_8BIT;
>> -               info->chipwidth = FLASH_CFI_BY8;
>> -               info->interface = FLASH_CFI_X8;
>> -               return 1;
>> -       } else {
>> -               return 0;
>> -       }
>> -}
>> -
>> -int board_eth_init(bd_t *bis)
>> -{
>> -       return pci_eth_init(bis);
>> -}
>> -
>> -void setup_pcat_compatibility()
>> -{
>> -       /* disable global interrupt mode */
>> -       writeb(0x40, &sc520_mmcr->picicr);
>> -
>> -       /* set all irqs to edge */
>> -       writeb(0x00, &sc520_mmcr->pic_mode[0]);
>> -       writeb(0x00, &sc520_mmcr->pic_mode[1]);
>> -       writeb(0x00, &sc520_mmcr->pic_mode[2]);
>> -
>> -       /*
>> -        *  active low polarity on PIC interrupt pins,
>> -        *  active high polarity on all other irq pins
>> -        */
>> -       writew(0x0000, &sc520_mmcr->intpinpol);
>> -
>> -       /*
>> -        * PIT 0 -> IRQ0
>> -        * RTC -> IRQ8
>> -        * FP error -> IRQ13
>> -        * UART1 -> IRQ4
>> -        * UART2 -> IRQ3
>> -        */
>> -       writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
>> -       writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
>> -       writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
>> -       writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
>> -       writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
>> -
>> -       /* Disable all other interrupt sources */
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
>> -       writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
>> -}
>> -
>> -void enet_timer_isr(void)
>> -{
>> -       static long enet_ticks;
>> -
>> -       enet_ticks++;
>> -
>> -       /* Toggle Watchdog every 100ms */
>> -       if ((enet_ticks % 100) == 0)
>> -               hw_watchdog_reset();
>> -
>> -       /* Toggle Run LED every 500ms */
>> -       if ((enet_ticks % 500) == 0)
>> -               enet_toggle_run_led();
>> -}
>> -
>> -void hw_watchdog_reset(void)
>> -{
>> -       /* Watchdog Reset must be atomic */
>> -       long flag = disable_interrupts();
>> -
>> -       if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
>> -               sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
>> -       else
>> -               sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
>> -
>> -       if (flag)
>> -               enable_interrupts();
>> -}
>> -
>> -void enet_toggle_run_led(void)
>> -{
>> -       unsigned char leds_state = inb(LED_LATCH_ADDRESS);
>> -       if (leds_state & LED_RUN_BITMASK)
>> -               outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
>> -       else
>> -               outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
>> -}
>> diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
>> deleted file mode 100644
>> index 5af4ef7..0000000
>> --- a/board/eNET/eNET_pci.c
>> +++ /dev/null
>> @@ -1,128 +0,0 @@
>> -/*
>> - * (C) Copyright 2008,2009
>> - * Graeme Russ, <graeme.russ@gmail.com>
>> - *
>> - * (C) Copyright 2002
>> - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -#include <common.h>
>> -#include <pci.h>
>> -#include <asm/pci.h>
>> -#include <asm/arch/pci.h>
>> -
>> -static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t
>> dev)
>> -{
>> -       /* a configurable lists of IRQs to steal when we need one */
>> -       static int irq_list[] = {
>> -               CONFIG_SYS_FIRST_PCI_IRQ,
>> -               CONFIG_SYS_SECOND_PCI_IRQ,
>> -               CONFIG_SYS_THIRD_PCI_IRQ,
>> -               CONFIG_SYS_FORTH_PCI_IRQ
>> -       };
>> -       static int next_irq_index;
>> -
>> -       uchar tmp_pin;
>> -       int pin;
>> -
>> -       pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
>> -       pin = tmp_pin;
>> -
>> -       pin -= 1; /* PCI config space use 1-based numbering */
>> -       if (pin == -1)
>> -               return; /* device use no irq */
>> -
>> -       /* map device number +  pin to a pin on the sc520 */
>> -       switch (PCI_DEV(dev)) {
>> -       case 12:        /* First Ethernet Chip */
>> -               pin += SC520_PCI_INTA;
>> -               break;
>> -
>> -       case 13:        /* Second Ethernet Chip */
>> -               pin += SC520_PCI_INTB;
>> -               break;
>> -
>> -       default:
>> -               return;
>> -       }
>> -
>> -       pin &= 3; /* wrap around */
>> -
>> -       if (sc520_pci_ints[pin] == -1) {
>> -               /* re-route one interrupt for us */
>> -               if (next_irq_index > 3)
>> -                       return;
>> -
>> -               if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
>> -                       return;
>> -
>> -               next_irq_index++;
>> -       }
>> -
>> -       if (-1 != sc520_pci_ints[pin])
>> -               pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
>> -                                          sc520_pci_ints[pin]);
>> -
>> -       printf("fixup_irq: device %d pin %c irq %d\n",
>> -              PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
>> -}
>> -
>> -static struct pci_controller enet_hose = {
>> -       fixup_irq: pci_enet_fixup_irq,
>> -};
>> -
>> -void pci_init_board(void)
>> -{
>> -       pci_sc520_init(&enet_hose);
>> -}
>> -
>> -int pci_set_regions(struct pci_controller *hose)
>> -{
>> -       /* System memory space */
>> -       pci_set_region(hose->regions + 0,
>> -                      SC520_PCI_MEMORY_BUS,
>> -                      SC520_PCI_MEMORY_PHYS,
>> -                      SC520_PCI_MEMORY_SIZE,
>> -                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
>> -
>> -       /* ISA/PCI memory space */
>> -       pci_set_region(hose->regions + 1,
>> -                      SC520_ISA_MEM_BUS,
>> -                      SC520_ISA_MEM_PHYS,
>> -                      SC520_ISA_MEM_SIZE,
>> -                      PCI_REGION_MEM);
>> -
>> -       /* PCI I/O space */
>> -       pci_set_region(hose->regions + 2,
>> -                      SC520_PCI_IO_BUS,
>> -                      SC520_PCI_IO_PHYS,
>> -                      SC520_PCI_IO_SIZE,
>> -                      PCI_REGION_IO);
>> -
>> -       /* ISA/PCI I/O space */
>> -       pci_set_region(hose->regions + 3,
>> -                      SC520_ISA_IO_BUS,
>> -                      SC520_ISA_IO_PHYS,
>> -                      SC520_ISA_IO_SIZE,
>> -                      PCI_REGION_IO);
>> -
>> -       return 4;
>> -}
>> diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
>> deleted file mode 100644
>> index 0dec7ea..0000000
>> --- a/board/eNET/eNET_start.S
>> +++ /dev/null
>> @@ -1,30 +0,0 @@
>> -/*
>> - * (C) Copyright 2008
>> - * Graeme Russ, graeme.russ@gmail.com.
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -#include "hardware.h"
>> -
>> -/* board early intialization */
>> -.globl early_board_init
>> -early_board_init:
>> -       /* No 32-bit board specific initialisation */
>> -       jmp     early_board_init_ret
>> diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
>> deleted file mode 100644
>> index 5e3f44c..0000000
>> --- a/board/eNET/eNET_start16.S
>> +++ /dev/null
>> @@ -1,87 +0,0 @@
>> -/*
>> - * (C) Copyright 2008
>> - * Graeme Russ, graeme.russ@gmail.com.
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -/*
>> - * 16bit initialization code.
>> - * This code have to map the area of the boot flash
>> - * that is used by U-boot to its final destination.
>> - */
>> -
>> -#include "config.h"
>> -#include "hardware.h"
>> -#include <asm/arch/sc520.h>
>> -#include <generated/asm-offsets.h>
>> -
>> -.text
>> -.section .start16, "ax"
>> -.code16
>> -.globl board_init16
>> -board_init16:
>> -       /* Alias MMCR to 0xdf000 */
>> -       movw    $0xfffc, %dx
>> -       movl    $0x800df0cb, %eax
>> -       outl    %eax, %dx
>> -
>> -       /* Set ds to point to MMCR alias */
>> -       movw    $0xdf00, %ax
>> -       movw    %ax, %ds
>> -
>> -       /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
>> -       movl    $GENERATED_SC520_PAR14, %edi
>> -       movl    $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
>> -       movl    %eax, (%di)
>> -
>> -       /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
>> -       movl    $GENERATED_SC520_PAR15, %edi
>> -       movl    $CONFIG_SYS_SC520_LLIO_PAR, %eax
>> -       movl    %eax, (%di)
>> -
>> -       /* Disabe MMCR alias */
>> -       movw    $0xfffc, %dx
>> -       movl    $0x000000cb, %eax
>> -       outl    %eax, %dx
>> -
>> -       jmp     board_init16_ret
>> -
>> -.section .bios, "ax"
>> -.code16
>> -.globl realmode_reset
>> -.hidden realmode_reset
>> -.type realmode_reset, @function
>> -realmode_reset:
>> -       /* Alias MMCR to 0xdf000 */
>> -       movw    $0xfffc, %dx
>> -       movl    $0x800df0cb, %eax
>> -       outl    %eax, %dx
>> -
>> -       /* Set ds to point to MMCR alias */
>> -       movw    $0xdf00, %ax
>> -       movw    %ax, %ds
>> -
>> -       /* issue software reset thorugh MMCR */
>> -       movl    $0xd72, %edi
>> -       movb    $0x01, %al
>> -       movb    %al, (%di)
>> -
>> -1:     hlt
>> -       jmp     1
>> diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
>> deleted file mode 100644
>> index dec2cd8..0000000
>> --- a/board/eNET/hardware.h
>> +++ /dev/null
>> @@ -1,36 +0,0 @@
>> -/*
>> - * (C) Copyright 2008
>> - * Graeme Russ, graeme.russ@gmail.com.
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -#ifndef HARDWARE_H_
>> -#define HARDWARE_H_
>> -
>> -#define LED_LATCH_ADDRESS      0x1002
>> -#define LED_RUN_BITMASK                0x01
>> -#define LED_1_BITMASK          0x02
>> -#define LED_2_BITMASK          0x04
>> -#define LED_RX_BITMASK         0x08
>> -#define LED_TX_BITMASK         0x10
>> -#define LED_ERR_BITMASK                0x20
>> -#define WATCHDOG_PIO_BIT       0x8000
>> -
>> -#endif /* HARDWARE_H_ */
>> diff --git a/boards.cfg b/boards.cfg
>> index cd220af..b1319aa 100644
>> --- a/boards.cfg
>> +++ b/boards.cfg
>> @@ -1123,7 +1123,5 @@ gr_ep2s60                    sparc       leon3
>> -                   gaisler
>>  grsim                        sparc       leon3       -
>> gaisler
>>  gr_xc3s_1500                 sparc       leon3       -
>> gaisler
>>  coreboot-x86                 x86         x86        coreboot
>> chromebook-x86 coreboot    coreboot:SYS_TEXT_BASE=0x01110000
>> -eNET                         x86         x86        eNET                -
>> sc520       eNET:SYS_TEXT_BASE=0x38040000
>> -eNET_SRAM                    x86         x86        eNET                -
>> sc520       eNET:SYS_TEXT_BASE=0x19000000
>>  # Target                     ARCH        CPU         Board name
>> Vendor                SoC         Options
>>
>> ########################################################################################################################
>> diff --git a/include/configs/eNET.h b/include/configs/eNET.h
>> deleted file mode 100644
>> index 28cf95b..0000000
>> --- a/include/configs/eNET.h
>> +++ /dev/null
>> @@ -1,619 +0,0 @@
>> -/*
>> - * (C) Copyright 2008
>> - * Graeme Russ, graeme.russ@gmail.com.
>> - *
>> - * See file CREDITS for list of people who contributed to this
>> - * project.
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> - * MA 02111-1307 USA
>> - */
>> -
>> -#include <asm/ibmpc.h>
>> -/*
>> - * board/config.h - configuration options, board specific
>> - */
>> -
>> -#ifndef __CONFIG_H
>> -#define __CONFIG_H
>> -
>> -/*
>> - * High Level Configuration Options
>> - * (easy to change)
>> - */
>> -#define CONFIG_SYS_SC520
>> -#define CONFIG_SYS_SC520_SSI
>> -#define CONFIG_SHOW_BOOT_PROGRESS
>> -#define CONFIG_LAST_STAGE_INIT
>> -
>> -/*-----------------------------------------------------------------------
>> - * Watchdog Configuration
>> - * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
>> - * bottom (processor) board MUST be removed!
>> - */
>> -#undef CONFIG_WATCHDOG
>> -#define CONFIG_HW_WATCHDOG
>> -
>> -/*-----------------------------------------------------------------------
>> - * Real Time Clock Configuration
>> - */
>> -#define CONFIG_RTC_MC146818
>> -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS         0
>> -
>> -/*-----------------------------------------------------------------------
>> - * Serial Configuration
>> - */
>> -#define CONFIG_CONS_INDEX                      1
>> -#define CONFIG_SYS_NS16550
>> -#define CONFIG_SYS_NS16550_SERIAL
>> -#define CONFIG_SYS_NS16550_REG_SIZE            1
>> -#define CONFIG_SYS_NS16550_CLK                 1843200
>> -#define CONFIG_BAUDRATE                                9600
>> -#define CONFIG_SYS_BAUDRATE_TABLE              {300, 600, 1200, 2400,
>> 4800, \
>> -                                                9600, 19200, 38400,
>> 115200}
>> -#define CONFIG_SYS_NS16550_COM1                        UART0_BASE
>> -#define CONFIG_SYS_NS16550_COM2                        UART1_BASE
>> -#define CONFIG_SYS_NS16550_COM3                        (0x1000 +
>> UART0_BASE)
>> -#define CONFIG_SYS_NS16550_COM4                        (0x1000 +
>> UART1_BASE)
>> -#define CONFIG_SYS_NS16550_PORT_MAPPED
>> -
>> -/*-----------------------------------------------------------------------
>> - * Video Configuration
>> - */
>> -#undef CONFIG_VIDEO
>> -#undef CONFIG_CFB_CONSOLE
>> -
>> -/*-----------------------------------------------------------------------
>> - * Command line configuration.
>> - */
>> -#include <config_cmd_default.h>
>> -
>> -#define CONFIG_CMD_BDI
>> -#define CONFIG_CMD_BOOTD
>> -#define CONFIG_CMD_CONSOLE
>> -#define CONFIG_CMD_DATE
>> -#define CONFIG_CMD_ECHO
>> -#define CONFIG_CMD_FLASH
>> -#define CONFIG_CMD_FPGA
>> -#define CONFIG_CMD_IMI
>> -#define CONFIG_CMD_IMLS
>> -#define CONFIG_CMD_IRQ
>> -#define CONFIG_CMD_ITEST
>> -#define CONFIG_CMD_LOADB
>> -#define CONFIG_CMD_LOADS
>> -#define CONFIG_CMD_MEMORY
>> -#define CONFIG_CMD_MISC
>> -#define CONFIG_CMD_NET
>> -#undef CONFIG_CMD_NFS
>> -#define CONFIG_CMD_PCI
>> -#define CONFIG_CMD_PING
>> -#define CONFIG_CMD_RUN
>> -#define CONFIG_CMD_SAVEENV
>> -#define CONFIG_CMD_SETGETDCR
>> -#define CONFIG_CMD_SOURCE
>> -#define CONFIG_CMD_XIMG
>> -#define CONFIG_CMD_ZBOOT
>> -
>> -#define CONFIG_BOOTDELAY                       15
>> -#define CONFIG_BOOTARGS
>> "root=/dev/mtdblock0 console=ttyS0,9600"
>> -
>> -#if defined(CONFIG_CMD_KGDB)
>> -#define CONFIG_KGDB_BAUDRATE                   115200
>> -#define CONFIG_KGDB_SER_INDEX                  2
>> -#endif
>> -
>> -/*
>> - * Miscellaneous configurable options
>> - */
>> -#define        CONFIG_SYS_LONGHELP
>> -#define        CONFIG_SYS_PROMPT                       "boot > "
>> -#define        CONFIG_SYS_CBSIZE                       256
>> -#define        CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE
>> + \
>> -                                                sizeof(CONFIG_SYS_PROMPT)
>> + \
>> -                                                16)
>> -#define        CONFIG_SYS_MAXARGS                      16
>> -#define CONFIG_SYS_BARGSIZE                    CONFIG_SYS_CBSIZE
>> -
>> -#define CONFIG_SYS_MEMTEST_START               0x00100000
>> -#define CONFIG_SYS_MEMTEST_END                 0x01000000
>> -#define        CONFIG_SYS_LOAD_ADDR                    0x100000
>> -#define        CONFIG_SYS_HZ                           1000
>> -
>> -/*-----------------------------------------------------------------------
>> - * SDRAM Configuration
>> - */
>> -#define CONFIG_SYS_SDRAM_DRCTMCTL              0x18
>> -#define CONFIG_SYS_SDRAM_REFRESH_RATE          156
>> -#define CONFIG_NR_DRAM_BANKS                   4
>> -
>> -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
>> -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
>> -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
>> -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
>> -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
>> -
>> -/*-----------------------------------------------------------------------
>> - * CPU Features
>> - */
>> -#define CONFIG_SYS_SC520_HIGH_SPEED            0
>> -#define CONFIG_SYS_SC520_RESET
>> -#define CONFIG_SYS_SC520_TIMER
>> -#undef  CONFIG_SYS_GENERIC_TIMER
>> -#define CONFIG_SYS_PCAT_INTERRUPTS
>> -#define CONFIG_SYS_NUM_IRQS                    16
>> -#define CONFIG_SYS_PC_BIOS
>> -#define CONFIG_SYS_PCI_BIOS
>> -#define CONFIG_SYS_X86_REALMODE
>> -#define CONFIG_SYS_X86_ISR_TIMER
>> -
>> -/*-----------------------------------------------------------------------
>> - * Memory organization:
>> - * 32kB Stack
>> - * 16kB Cache-As-RAM @ 0x19200000
>> - * 256kB Monitor
>> - * (128kB + Environment Sector Size) malloc pool
>> - */
>> -#define CONFIG_SYS_STACK_SIZE                  (32 * 1024)
>> -#define CONFIG_SYS_CAR_ADDR                    0x19200000
>> -#define CONFIG_SYS_CAR_SIZE                    (16 * 1024)
>> -#define CONFIG_SYS_MONITOR_BASE
>> CONFIG_SYS_TEXT_BASE
>> -#define CONFIG_SYS_MONITOR_LEN                 (256 * 1024)
>> -#define CONFIG_SYS_MALLOC_LEN                  (CONFIG_ENV_SECT_SIZE + \
>> -                                                128*1024)
>> -/* allow to overwrite serial and ethaddr */
>> -#define CONFIG_ENV_OVERWRITE
>> -
>> -/*-----------------------------------------------------------------------
>> - * FLASH configuration
>> - * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
>> - * 16MB StrataFlash #1 @ 0x10000000
>> - * 16MB StrataFlash #2 @ 0x11000000
>> - */
>> -#define CONFIG_FLASH_CFI_DRIVER
>> -#define CONFIG_FLASH_CFI_LEGACY
>> -#define CONFIG_SYS_FLASH_CFI
>> -#define CONFIG_SYS_MAX_FLASH_BANKS             3
>> -#define CONFIG_SYS_FLASH_BASE                  0x38000000
>> -#define CONFIG_SYS_FLASH_BASE_1                        0x10000000
>> -#define CONFIG_SYS_FLASH_BASE_2                        0x11000000
>> -#define CONFIG_SYS_FLASH_BANKS_LIST            {CONFIG_SYS_FLASH_BASE,
>> \
>> -                                                CONFIG_SYS_FLASH_BASE_1,
>> \
>> -                                                CONFIG_SYS_FLASH_BASE_2}
>> -#define CONFIG_SYS_FLASH_EMPTY_INFO
>> -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
>> -#define CONFIG_SYS_MAX_FLASH_SECT              128
>> -#define CONFIG_SYS_FLASH_CFI_WIDTH             FLASH_CFI_8BIT
>> -#define CONFIG_SYS_FLASH_LEGACY_512Kx8
>> -#define CONFIG_SYS_FLASH_ERASE_TOUT            2000    /* ms */
>> -#define CONFIG_SYS_FLASH_WRITE_TOUT            2000    /* ms */
>> -
>> -/*-----------------------------------------------------------------------
>> - * Environment configuration
>> - * - Boot flash is 512kB with 64kB sectors
>> - * - StrataFlash is 32MB with 128kB sectors
>> - * - Redundant embedded environment is 25% of the Boot flash
>> - * - Redundant StrataFlash environment is <1% of the StrataFlash
>> - * - Environment is therefore located in StrataFlash
>> - * - Primary copy is located in first sector of first flash
>> - * - Redundant copy is located in second sector of first flash
>> - * - Stack is only 32kB, so environment size is limited to 4kB
>> - */
>> -#define CONFIG_ENV_IS_IN_FLASH
>> -#define CONFIG_ENV_SECT_SIZE                   0x20000
>> -#define CONFIG_ENV_SIZE                                0x01000
>> -#define CONFIG_ENV_ADDR
>> CONFIG_SYS_FLASH_BASE_1
>> -#define CONFIG_ENV_ADDR_REDUND                 (CONFIG_SYS_FLASH_BASE_1 +
>> \
>> -                                                CONFIG_ENV_SECT_SIZE)
>> -#define CONFIG_ENV_SIZE_REDUND                 CONFIG_ENV_SIZE
>> -
>> -/*-----------------------------------------------------------------------
>> - * PCI configuration
>> - */
>> -#define CONFIG_PCI
>> -#define CONFIG_PCI_PNP
>> -#define CONFIG_SYS_FIRST_PCI_IRQ               10
>> -#define CONFIG_SYS_SECOND_PCI_IRQ              9
>> -#define CONFIG_SYS_THIRD_PCI_IRQ               11
>> -#define CONFIG_SYS_FORTH_PCI_IRQ               15
>> -
>> -/*-----------------------------------------------------------------------
>> - * Network device (TRL8100B) support
>> - */
>> -#define CONFIG_RTL8139
>> -
>> -/*-----------------------------------------------------------------------
>> - * BOOTCS Control (for AM29LV040B-120JC)
>> - *
>> - * 000 0 00 0 000 11 0 011 }- 0x0033
>> - * \ / | \| | \ / \| | \ /
>> - *  |  |  | |  |   | |  |
>> - *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
>> - *  |  |  | |  |   | +------- Reserved
>> - *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
>> - *  |  |  | |  +------------- Reserved
>> - *  |  |  | +---------------- Non-Paged Mode
>> - *  |  |  +------------------ 8 Bit Wide
>> - *  |  +--------------------- GP Bus
>> - *  +------------------------ Reserved
>> - */
>> -#define CONFIG_SYS_SC520_BOOTCS_CTRL           0x0033
>> -
>> -/*-----------------------------------------------------------------------
>> - * ROMCS Control (for E28F128J3A-150 StrataFlash)
>> - *
>> - * 000 0 01 1 000 01 0 101 }- 0x0615
>> - * \ / | \| | \ / \| | \ /
>> - *  |  |  | |  |   | |  |
>> - *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
>> - *  |  |  | |  |   | +------- Reserved
>> - *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
>> - *  |  |  | |  +------------- Reserved
>> - *  |  |  | +---------------- Paged Mode
>> - *  |  |  +------------------ 16 Bit Wide
>> - *  |  +--------------------- GP Bus
>> - *  +------------------------ Reserved
>> - */
>> -#define CONFIG_SYS_SC520_ROMCS1_CTRL           0x0615
>> -#define CONFIG_SYS_SC520_ROMCS2_CTRL           0x0615
>> -
>> -/*-----------------------------------------------------------------------
>> - * SC520 General Purpose Bus configuration
>> - *
>> - * Chip Select Offset          1 Clock Cycle
>> - * Chip Select Pulse Width     8 Clock Cycles
>> - * Chip Select Read Offset     2 Clock Cycles
>> - * Chip Select Read Width      6 Clock Cycles
>> - * Chip Select Write Offset    2 Clock Cycles
>> - * Chip Select Write Width     6 Clock Cycles
>> - * Chip Select Recovery Time   2 Clock Cycles
>> - *
>> - * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
>> - *
>> - *   |<-------------General Purpose Bus Cycle---------------->|
>> - *   |                                                        |
>> - * ----------------------\__________________/------------------
>> - *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
>> - *
>> - * ------------------------\_______________/-------------------
>> - *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
>> - *
>> - * --------------------------\_______________/-----------------
>> - *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
>> - *
>> - * ________/-----------\_______________________________________
>> - *   |<--->|<--------->|
>> - *      ^         ^
>> - * (GPALEOFF + 1) |
>> - *                |
>> - *         (GPALEW + 1)
>> - */
>> -#define CONFIG_SYS_SC520_GPCSOFF               0x00
>> -#define CONFIG_SYS_SC520_GPCSPW                        0x07
>> -#define CONFIG_SYS_SC520_GPRDOFF               0x01
>> -#define CONFIG_SYS_SC520_GPRDW                 0x05
>> -#define CONFIG_SYS_SC520_GPWROFF               0x01
>> -#define CONFIG_SYS_SC520_GPWRW                 0x05
>> -#define CONFIG_SYS_SC520_GPCSRT                        0x01
>> -
>> -/*-----------------------------------------------------------------------
>> - * SC520 Programmable I/O configuration
>> - *
>> - * Pin   Mode          Dir.    Description
>> - * ----------------------------------------------------------------------
>> - * PIO0   PIO          Output  Unused
>> - * PIO1   GPBHE#       Output  GP Bus Byte High Enable (active low)
>> - * PIO2   PIO          Output  Auxiliary power output enable
>> - * PIO3   GPAEN                Output  GP Bus Address Enable
>> - * PIO4   PIO          Output  Top Board Enable (active low)
>> - * PIO5   PIO          Output  StrataFlash 16 bit mode (low = 8 bit mode)
>> - * PIO6   PIO          Input   Data output of Power Supply ADC
>> - * PIO7   PIO          Output  Clock input to Power Supply ADC
>> - * PIO8   PIO          Output  Chip Select input of Power Supply ADC
>> - * PIO9   PIO          Output  StrataFlash 1 Reset / Power Down (active
>> low)
>> - * PIO10  PIO          Output  StrataFlash 2 Reset / Power Down (active
>> low)
>> - * PIO11  PIO          Input   StrataFlash 1 Status
>> - * PIO12  PIO          Input   StrataFlash 2 Status
>> - * PIO13  GPIRQ10#     Input   Can Bus / I2C IRQ (active low)
>> - * PIO14  PIO          Input   Low Input Voltage Warning (active low)
>> - * PIO15  PIO          Output  Watchdog (must toggle at least every 1.6s)
>> - * PIO16  PIO          Input   Power Fail
>> - * PIO17  GPIRQ6       Input   Compact Flash 1 IRQ (active low)
>> - * PIO18  GPIRQ5       Input   Compact Flash 2 IRQ (active low)
>> - * PIO19  GPIRQ4#      Input   Dual-Port RAM IRQ (active low)
>> - * PIO20  GPIRQ3       Input   UART D IRQ
>> - * PIO21  GPIRQ2       Input   UART C IRQ
>> - * PIO22  GPIRQ1       Input   UART B IRQ
>> - * PIO23  GPIRQ0       Input   UART A IRQ
>> - * PIO24  GPDBUFOE#    Output  GP Bus Data Bus Buffer Output Enable
>> - * PIO25  PIO          Input   Battery OK Indication
>> - * PIO26  GPMEMCS16#   Input   GP Bus Memory Chip-Select 16-bit access
>> - * PIO27  GPCS0#       Output  SRAM 1 Chip Select
>> - * PIO28  PIO          Input   Top Board UART CTS
>> - * PIO29  PIO          Output  FPGA Program Mode (active low)
>> - * PIO30  PIO          Input   FPGA Initialised (active low)
>> - * PIO31  PIO          Input   FPGA Done (active low)
>> - */
>> -#define CONFIG_SYS_SC520_PIOPFS15_0            0x200a
>> -#define CONFIG_SYS_SC520_PIOPFS31_16           0x0dfe
>> -#define CONFIG_SYS_SC520_PIODIR15_0            0x87bf
>> -#define CONFIG_SYS_SC520_PIODIR31_16           0x2900
>> -
>> -/*-----------------------------------------------------------------------
>> - * PIO Pin defines
>> - */
>> -#define CONFIG_SYS_ENET_AUX_PWR                        0x0004
>> -#define CONFIG_SYS_ENET_TOP_BRD_PWR            0x0010
>> -#define CONFIG_SYS_ENET_SF_WIDTH               0x0020
>> -#define CONFIG_SYS_ENET_PWR_ADC_DATA           0x0040
>> -#define CONFIG_SYS_ENET_PWR_ADC_CLK            0x0080
>> -#define CONFIG_SYS_ENET_PWR_ADC_CS             0x0100
>> -#define CONFIG_SYS_ENET_SF1_MODE               0x0200
>> -#define CONFIG_SYS_ENET_SF2_MODE               0x0400
>> -#define CONFIG_SYS_ENET_SF1_STATUS             0x0800
>> -#define CONFIG_SYS_ENET_SF2_STATUS             0x1000
>> -#define CONFIG_SYS_ENET_PWR_STATUS             0x4000
>> -#define CONFIG_SYS_ENET_WATCHDOG               0x8000
>> -
>> -#define CONFIG_SYS_ENET_PWR_FAIL               0x0001
>> -#define CONFIG_SYS_ENET_BAT_OK                 0x0200
>> -#define CONFIG_SYS_ENET_TOP_BRD_CTS            0x1000
>> -#define CONFIG_SYS_ENET_FPGA_PROG              0x2000
>> -#define CONFIG_SYS_ENET_FPGA_INIT              0x4000
>> -#define CONFIG_SYS_ENET_FPGA_DONE              0x8000
>> -
>> -/*-----------------------------------------------------------------------
>> - * Chip Select Pin Function Select
>> - *
>> - * 1 1 1 1 1 0 0 0 }- 0xf8
>> - * | | | | | | | |
>> - * | | | | | | | +--- Reserved
>> - * | | | | | | +----- GPCS1_SEL = ROMCS1#
>> - * | | | | | +------- GPCS2_SEL = ROMCS2#
>> - * | | | | +--------- GPCS3_SEL = GPCS3
>> - * | | | +----------- GPCS4_SEL = GPCS4
>> - * | | +------------- GPCS5_SEL = GPCS5
>> - * | +--------------- GPCS6_SEL = GPCS6
>> - * +----------------- GPCS7_SEL = GPCS7
>> - */
>> -#define CONFIG_SYS_SC520_CSPFS                 0xf8
>> -
>> -/*-----------------------------------------------------------------------
>> - * Clock Select (CLKTIMER[CLKTEST] pin)
>> - *
>> - * 0 111 00 1 0 }- 0x72
>> - * | \ / \| | |
>> - * |  |   | | +--- Pin Disabled
>> - * |  |   | +----- Pin is an output
>> - * |  |   +------- Reserved
>> - * |  +----------- Disabled (pin stays Low)
>> - * +-------------- Reserved
>> - */
>> -#define CONFIG_SYS_SC520_CLKSEL                        0x72
>> -
>> -/*-----------------------------------------------------------------------
>> - * Address Decode Control
>> - *
>> - * 0 00 0 0 0 0 0 }- 0x00
>> - * | \| | | | | |
>> - * |  | | | | | +--- Integrated UART 1 is enabled
>> - * |  | | | | +----- Integrated UART 2 is enabled
>> - * |  | | | +------- Integrated RTC is enabled
>> - * |  | | +--------- Reserved
>> - * |  | +----------- I/O Hole accesses are forwarded to the external GP
>> bus
>> - * |  +------------- Reserved
>> - * +---------------- Write-protect violations do not generate an IRQ
>> - */
>> -#define CONFIG_SYS_SC520_ADDDECCTL             0x00
>> -
>> -/*-----------------------------------------------------------------------
>> - * UART Control
>> - *
>> - * 00000 1 1 1 }- 0x07
>> - * \___/ | | |
>> - *   |   | | +--- Transmit TC interrupt enable
>> - *   |   | +----- Receive TC interrupt enable
>> - *   |   +------- 1.8432 MHz
>> - *   +----------- Reserved
>> - */
>> -#define CONFIG_SYS_SC520_UART1CTL              0x07
>> -#define CONFIG_SYS_SC520_UART2CTL              0x07
>> -
>> -/*-----------------------------------------------------------------------
>> - * System Arbiter Control
>> - *
>> - * 00000 1 1 0 }- 0x06
>> - * \___/ | | |
>> - *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
>> - *   |   | +----- The system arbiter operates in concurrent mode
>> - *   |   +------- Park the PCI bus on the last master that acquired the
>> bus
>> - *   +----------- Reserved
>> - */
>> -#define CONFIG_SYS_SC520_SYSARBCTL             0x06
>> -
>> -/*-----------------------------------------------------------------------
>> - * System Arbiter Master Enable
>> - *
>> - * 00000000000 0 0 0 1 1 }- 0x06
>> - * \_________/ | | | | |
>> - *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
>> - *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
>> - *      |      | | +------- PCI master REQ2 disabled
>> - *      |      | +--------- PCI master REQ3 disabled
>> - *      |      +----------- PCI master REQ4 disabled
>> - *      +------------------ Reserved
>> - */
>> -#define CONFIG_SYS_SC520_SYSARBMENB            0x0003
>> -
>> -/*-----------------------------------------------------------------------
>> - * System Arbiter Master Enable
>> - *
>> - * 0 0000 0 00 0000 1 000 }- 0x06
>> - * | \__/ | \| \__/ | \_/
>> - * |   |  |  |   |  |  +---- Reserved
>> - * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
>> - * |   |  |  |   +---------- Reserved
>> - * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
>> - * |   |  |                  retried
>> - * |   |  +----------------- Target read FIFOs are not snooped during
>> write
>> - * |   |                     transactions
>> - * |   +-------------------- Reserved
>> - * +------------------------ Deassert the PCI bus reset signal
>> - */
>> -#define CONFIG_SYS_SC520_HBCTL                 0x08
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
>> - * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
>> - * \ / | | | | \----+----/ \-----+------/
>> - *  |  | | | |      |            +---------- Start at 0x38000000
>> - *  |  | | | |      +----------------------- 512kB Region Size
>> - *  |  | | | |                               ((7 + 1) * 64kB)
>> - *  |  | | | +------------------------------ 64kB Page Size
>> - *  |  | | +-------------------------------- Writes Enabled (So it can be
>> - *  |  | |                                   reprogrammed!)
>> - *  |  | +---------------------------------- Caching Disabled
>> - *  |  +------------------------------------ Execution Enabled
>> - *  +--------------------------------------- BOOTCS
>> - */
>> -#define CONFIG_SYS_SC520_BOOTCS_PAR            0x8a01f800
>> -
>> -/*-----------------------------------------------------------------------
>> - * Cache-As-RAM (Targets Boot Flash)
>> - *
>> - * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
>> - * \ / | | | | \--+--/ \-------+--------/
>> - *  |  | | | |    |            +------------ Start at 0x19200000
>> - *  |  | | | |    +------------------------- 64k Region Size
>> - *  |  | | | |                               ((15 + 1) * 4kB)
>> - *  |  | | | +------------------------------ 4kB Page Size
>> - *  |  | | +-------------------------------- Writes Enabled
>> - *  |  | +---------------------------------- Caching Enabled
>> - *  |  +------------------------------------ Execution Prevented
>> - *  +--------------------------------------- BOOTCS
>> - */
>> -#define CONFIG_SYS_SC520_CAR_PAR               0x903d9200
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000,
>> GPCS6
>> - *
>> - * 001 110 0 000100000 0001000000000000 }- 0x38201000
>> - * \ / \ / | \---+---/ \------+-------/
>> - *  |   |  |     |            +----------- Start at 0x00001000
>> - *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
>> - *  |   |  +------------------------------ Ignored
>> - *  |   +--------------------------------- GPCS6
>> - *  +------------------------------------- GP Bus I/O
>> - */
>> -#define CONFIG_SYS_SC520_LLIO_PAR              0x38201000
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
>> - * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
>> - *
>> - * 010 101 0 0000000 100000000000000000 }- 0x54020000
>> - * 010 111 0 0000000 100000000000000001 }- 0x5c020001
>> - * \ / \ / | \--+--/ \-------+--------/
>> - *  |   |  |    |            +------------ Start at 0x200000000
>> - *  |   |  |    |                                   0x200010000
>> - *  |   |  |    +------------------------- 4kB Region Size
>> - *  |   |  |                               ((0 + 1) * 4kB)
>> - *  |   |  +------------------------------ 4k Page Size
>> - *  |   +--------------------------------- GPCS5
>> - *  |                                      GPCS7
>> - *  +------------------------------------- GP Bus Memory
>> - */
>> -#define CONFIG_SYS_SC520_CF1_PAR               0x54020000
>> -#define CONFIG_SYS_SC520_CF2_PAR               0x5c020001
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
>> - * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
>> - * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
>> - * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
>> - *
>> - * 001 000 0 000000111 0001001111111000 }- 0x200713f8
>> - * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
>> - * 001 011 0 000000111 0001001011111000 }- 0x300711f8
>> - * 001 011 0 000000111 0001001011111000 }- 0x340710f8
>> - * \ / \ / | \---+---/ \------+-------/
>> - *  |   |  |     |            +----------- Start at 0x013f8
>> - *  |   |  |     |                                  0x012f8
>> - *  |   |  |     |                                  0x011f8
>> - *  |   |  |     |                                  0x010f8
>> - *  |   |  |     +------------------------ 33 Bytes (32 + 1)
>> - *  |   |  +------------------------------ Ignored
>> - *  |   +--------------------------------- GPCS6
>> - *  +------------------------------------- GP Bus I/O
>> - */
>> -#define CONFIG_SYS_SC520_UARTA_PAR             0x200713f8
>> -#define CONFIG_SYS_SC520_UARTB_PAR             0x2c0712f8
>> -#define CONFIG_SYS_SC520_UARTC_PAR             0x300711f8
>> -#define CONFIG_SYS_SC520_UARTD_PAR             0x340710f8
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
>> - * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
>> - *
>> - * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
>> - * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
>> - * \ / | | | | \----+----/ \-----+------/
>> - *  |  | | | |      |            +---------- Start at 0x10000000
>> - *  |  | | | |      |                                 0x11000000
>> - *  |  | | | |      +----------------------- 16MB Region Size
>> - *  |  | | | |                               ((255 + 1) * 64kB)
>> - *  |  | | | +------------------------------ 64kB Page Size
>> - *  |  | | +-------------------------------- Writes Enabled
>> - *  |  | +---------------------------------- Caching Disabled
>> - *  |  +------------------------------------ Execution Enabled
>> - *  +--------------------------------------- ROMCS1
>> - *                                           ROMCS2
>> - */
>> -#define CONFIG_SYS_SC520_SF1_PAR               0xaa3fd000
>> -#define CONFIG_SYS_SC520_SF2_PAR               0xca3fd100
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
>> - * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
>> - *
>> - * 010 000 1 00000001111 01100100000000 }- 0x4203d900
>> - * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
>> - * \ / \ / | \----+----/ \-----+------/
>> - *  |   |  |      |            +---------- Start at 0x19000000
>> - *  |   |  |      |                                 0x19100000
>> - *  |   |  |      +----------------------- 1MB Region Size
>> - *  |   |  |                               ((15 + 1) * 64kB)
>> - *  |   |  +------------------------------ 64kB Page Size
>> - *  |   +--------------------------------- GPCS0
>> - *  |                                      GPCS3
>> - *  +------------------------------------- GP Bus Memory
>> - */
>> -#define CONFIG_SYS_SC520_SRAM1_PAR             0x4203d900
>> -#define CONFIG_SYS_SC520_SRAM2_PAR             0x4e03d910
>> -
>> -/*-----------------------------------------------------------------------
>> - * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
>> - *
>> - * 010 100 0 00000000 11000000100000000 }- 0x50018100
>> - * \ / \ / | \---+--/ \-------+-------/
>> - *  |   |  |     |            +----------- Start at 0x18100000
>> - *  |   |  |     +------------------------ 4kB Region Size
>> - *  |   |  |                               ((0 + 1) * 4kB)
>> - *  |   |  +------------------------------ 4kB Page Size
>> - *  |   +--------------------------------- GPCS4
>> - *  +------------------------------------- GP Bus Memory
>> - */
>> -#define CONFIG_SYS_SC520_DPRAM_PAR             0x50018100
>> -
>> -#endif /* __CONFIG_H */
>> --
>> 1.8.1
>>
>

Patch

diff --git a/board/eNET/Makefile b/board/eNET/Makefile
deleted file mode 100644
index ad1c5b1..0000000
--- a/board/eNET/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@ 
-#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= eNET.o
-COBJS-$(CONFIG_PCI) += eNET_pci.o
-SOBJS-y	+= eNET_start16.o
-SOBJS-y	+= eNET_start.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
deleted file mode 100644
index 2f26470..0000000
--- a/board/eNET/eNET.c
+++ /dev/null
@@ -1,284 +0,0 @@ 
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
-#include <net.h>
-#include <netdev.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-#include "hardware.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-static void enet_timer_isr(void);
-static void enet_toggle_run_led(void);
-static void enet_setup_pars(void);
-
-/*
- * Miscellaneous platform dependent initializations
- */
-int board_early_init_f(void)
-{
-	u16 pio_out_cfg = 0x0000;
-
-	/* Configure General Purpose Bus timing */
-	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
-	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
-	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
-	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
-	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
-	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
-	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
-
-	/* Configure Programmable Input/Output Pins */
-	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
-	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
-	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
-	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
-	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
-
-	/*
-	 * Turn off top board
-	 * Set StrataFlash chips to 16-bit width
-	 * Set StrataFlash chips to normal (non reset/power down) mode
-	 */
-	pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
-	pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
-	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
-
-	/* Turn off auxiliary power output */
-	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
-
-	/* Clear FPGA program mode */
-	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
-
-	enet_setup_pars();
-
-	/* Disable Watchdog */
-	writew(0x3333, &sc520_mmcr->wdtmrctl);
-	writew(0xcccc, &sc520_mmcr->wdtmrctl);
-	writew(0x0000, &sc520_mmcr->wdtmrctl);
-
-	/* Chip Select Configuration */
-	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
-	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
-	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
-
-	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
-	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
-	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
-
-	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
-	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
-
-	/* enable posted-writes */
-	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
-
-	return 0;
-}
-
-static void enet_setup_pars(void)
-{
-	/*
-	 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
-	 *
-	 * These are setup now because older version of U-Boot have them
-	 * mapped to a different PAR which gets clobbered which prevents
-	 * using SRAM for warm-booting a new image
-	 */
-	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
-	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
-
-	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
-	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
-	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
-
-	/* PAR 2 is used for Cache-As-RAM */
-
-	/*
-	 * PARs 5 through 8 are additional NS16550 UARTS
-	 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
-	 */
-	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
-	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
-	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
-	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
-
-	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
-	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
-	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
-
-	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
-	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
-
-	/*
-	 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
-	 * Already configured in board_init16 (eNET_start16.S)
-	 *
-	 * PAR 15 is Boot ROM
-	 * Already configured in board_init16 (eNET_start16.S)
-	 */
-}
-
-
-int board_early_init_r(void)
-{
-	/* CPU Speed to 100MHz */
-	gd->cpu_clk = 100000000;
-
-	/* Crystal is 33.000MHz */
-	gd->bus_clk = 33000000;
-
-	return 0;
-}
-
-void show_boot_progress(int val)
-{
-	uchar led_mask;
-
-	led_mask = 0x00;
-
-	if (val < 0)
-		led_mask |= LED_ERR_BITMASK;
-
-	led_mask |= (uchar)(val & 0x001f);
-	outb(led_mask, LED_LATCH_ADDRESS);
-}
-
-
-int last_stage_init(void)
-{
-	outb(0x00, LED_LATCH_ADDRESS);
-
-	register_timer_isr(enet_timer_isr);
-
-	printf("Serck Controls eNET\n");
-
-	return 0;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = FLASH_CFI_8BIT;
-		info->chipwidth = FLASH_CFI_BY8;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void setup_pcat_compatibility()
-{
-	/* disable global interrupt mode */
-	writeb(0x40, &sc520_mmcr->picicr);
-
-	/* set all irqs to edge */
-	writeb(0x00, &sc520_mmcr->pic_mode[0]);
-	writeb(0x00, &sc520_mmcr->pic_mode[1]);
-	writeb(0x00, &sc520_mmcr->pic_mode[2]);
-
-	/*
-	 *  active low polarity on PIC interrupt pins,
-	 *  active high polarity on all other irq pins
-	 */
-	writew(0x0000, &sc520_mmcr->intpinpol);
-
-	/*
-	 * PIT 0 -> IRQ0
-	 * RTC -> IRQ8
-	 * FP error -> IRQ13
-	 * UART1 -> IRQ4
-	 * UART2 -> IRQ3
-	 */
-	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
-	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
-	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
-	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
-	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
-
-	/* Disable all other interrupt sources */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
-}
-
-void enet_timer_isr(void)
-{
-	static long enet_ticks;
-
-	enet_ticks++;
-
-	/* Toggle Watchdog every 100ms */
-	if ((enet_ticks % 100) == 0)
-		hw_watchdog_reset();
-
-	/* Toggle Run LED every 500ms */
-	if ((enet_ticks % 500) == 0)
-		enet_toggle_run_led();
-}
-
-void hw_watchdog_reset(void)
-{
-	/* Watchdog Reset must be atomic */
-	long flag = disable_interrupts();
-
-	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
-		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
-	else
-		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
-
-	if (flag)
-		enable_interrupts();
-}
-
-void enet_toggle_run_led(void)
-{
-	unsigned char leds_state = inb(LED_LATCH_ADDRESS);
-	if (leds_state & LED_RUN_BITMASK)
-		outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-	else
-		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-}
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
deleted file mode 100644
index 5af4ef7..0000000
--- a/board/eNET/eNET_pci.c
+++ /dev/null
@@ -1,128 +0,0 @@ 
-/*
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-
-static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* a configurable lists of IRQs to steal when we need one */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin -= 1; /* PCI config space use 1-based numbering */
-	if (pin == -1)
-		return; /* device use no irq */
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 12:	/* First Ethernet Chip */
-		pin += SC520_PCI_INTA;
-		break;
-
-	case 13:	/* Second Ethernet Chip */
-		pin += SC520_PCI_INTB;
-		break;
-
-	default:
-		return;
-	}
-
-	pin &= 3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3)
-			return;
-
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
-			return;
-
-		next_irq_index++;
-	}
-
-	if (-1 != sc520_pci_ints[pin])
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-
-	printf("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller enet_hose = {
-	fixup_irq: pci_enet_fixup_irq,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&enet_hose);
-}
-
-int pci_set_regions(struct pci_controller *hose)
-{
-	/* System memory space */
-	pci_set_region(hose->regions + 0,
-		       SC520_PCI_MEMORY_BUS,
-		       SC520_PCI_MEMORY_PHYS,
-		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* ISA/PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       SC520_ISA_MEM_BUS,
-		       SC520_ISA_MEM_PHYS,
-		       SC520_ISA_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(hose->regions + 2,
-		       SC520_PCI_IO_BUS,
-		       SC520_PCI_IO_PHYS,
-		       SC520_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* ISA/PCI I/O space */
-	pci_set_region(hose->regions + 3,
-		       SC520_ISA_IO_BUS,
-		       SC520_ISA_IO_PHYS,
-		       SC520_ISA_IO_SIZE,
-		       PCI_REGION_IO);
-
-	return 4;
-}
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
deleted file mode 100644
index 0dec7ea..0000000
--- a/board/eNET/eNET_start.S
+++ /dev/null
@@ -1,30 +0,0 @@ 
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include "hardware.h"
-
-/* board early intialization */
-.globl early_board_init
-early_board_init:
-	/* No 32-bit board specific initialisation */
-	jmp	early_board_init_ret
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
deleted file mode 100644
index 5e3f44c..0000000
--- a/board/eNET/eNET_start16.S
+++ /dev/null
@@ -1,87 +0,0 @@ 
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-#include "config.h"
-#include "hardware.h"
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
-	movl    $GENERATED_SC520_PAR14, %edi
-	movl	$CONFIG_SYS_SC520_BOOTCS_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
-	movl    $GENERATED_SC520_PAR15, %edi
-	movl	$CONFIG_SYS_SC520_LLIO_PAR, %eax
-	movl	%eax, (%di)
-
-	/* Disabe MMCR alias */
-	movw	$0xfffc, %dx
-	movl	$0x000000cb, %eax
-	outl	%eax, %dx
-
-	jmp	board_init16_ret
-
-.section .bios, "ax"
-.code16
-.globl realmode_reset
-.hidden realmode_reset
-.type realmode_reset, @function
-realmode_reset:
-	/* Alias MMCR to 0xdf000 */
-	movw	$0xfffc, %dx
-	movl	$0x800df0cb, %eax
-	outl	%eax, %dx
-
-	/* Set ds to point to MMCR alias */
-	movw	$0xdf00, %ax
-	movw	%ax, %ds
-
-	/* issue software reset thorugh MMCR */
-	movl    $0xd72, %edi
-	movb	$0x01, %al
-	movb	%al, (%di)
-
-1:	hlt
-	jmp	1
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
deleted file mode 100644
index dec2cd8..0000000
--- a/board/eNET/hardware.h
+++ /dev/null
@@ -1,36 +0,0 @@ 
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef HARDWARE_H_
-#define HARDWARE_H_
-
-#define LED_LATCH_ADDRESS	0x1002
-#define LED_RUN_BITMASK		0x01
-#define LED_1_BITMASK		0x02
-#define LED_2_BITMASK		0x04
-#define LED_RX_BITMASK		0x08
-#define LED_TX_BITMASK		0x10
-#define LED_ERR_BITMASK		0x20
-#define WATCHDOG_PIO_BIT	0x8000
-
-#endif /* HARDWARE_H_ */
diff --git a/boards.cfg b/boards.cfg
index cd220af..b1319aa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1123,7 +1123,5 @@  gr_ep2s60                    sparc       leon3       -                   gaisler
 grsim                        sparc       leon3       -                   gaisler
 gr_xc3s_1500                 sparc       leon3       -                   gaisler
 coreboot-x86                 x86         x86        coreboot            chromebook-x86 coreboot    coreboot:SYS_TEXT_BASE=0x01110000
-eNET                         x86         x86        eNET                -              sc520       eNET:SYS_TEXT_BASE=0x38040000
-eNET_SRAM                    x86         x86        eNET                -              sc520       eNET:SYS_TEXT_BASE=0x19000000
 # Target                     ARCH        CPU         Board name          Vendor	        SoC         Options
 ########################################################################################################################
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
deleted file mode 100644
index 28cf95b..0000000
--- a/include/configs/eNET.h
+++ /dev/null
@@ -1,619 +0,0 @@ 
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/ibmpc.h>
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_SC520
-#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_LAST_STAGE_INIT
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
- * bottom (processor) board MUST be removed!
- */
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		0
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CONFIG_CONS_INDEX			1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE		1
-#define CONFIG_SYS_NS16550_CLK			1843200
-#define CONFIG_BAUDRATE				9600
-#define CONFIG_SYS_BAUDRATE_TABLE		{300, 600, 1200, 2400, 4800, \
-						 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1			UART0_BASE
-#define CONFIG_SYS_NS16550_COM2			UART1_BASE
-#define CONFIG_SYS_NS16550_COM3			(0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4			(0x1000 + UART1_BASE)
-#define CONFIG_SYS_NS16550_PORT_MAPPED
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMLS
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_ZBOOT
-
-#define CONFIG_BOOTDELAY			15
-#define CONFIG_BOOTARGS				"root=/dev/mtdblock0 console=ttyS0,9600"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE			115200
-#define CONFIG_KGDB_SER_INDEX			2
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP
-#define	CONFIG_SYS_PROMPT			"boot > "
-#define	CONFIG_SYS_CBSIZE			256
-#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
-						 sizeof(CONFIG_SYS_PROMPT) + \
-						 16)
-#define	CONFIG_SYS_MAXARGS			16
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00100000
-#define CONFIG_SYS_MEMTEST_END			0x01000000
-#define	CONFIG_SYS_LOAD_ADDR			0x100000
-#define	CONFIG_SYS_HZ				1000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_SYS_SDRAM_DRCTMCTL		0x18
-#define CONFIG_SYS_SDRAM_REFRESH_RATE		156
-#define CONFIG_NR_DRAM_BANKS			4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-#define CONFIG_SYS_SC520_HIGH_SPEED		0
-#define CONFIG_SYS_SC520_RESET
-#define CONFIG_SYS_SC520_TIMER
-#undef  CONFIG_SYS_GENERIC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_NUM_IRQS			16
-#define CONFIG_SYS_PC_BIOS
-#define CONFIG_SYS_PCI_BIOS
-#define CONFIG_SYS_X86_REALMODE
-#define CONFIG_SYS_X86_ISR_TIMER
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
-#define CONFIG_SYS_CAR_ADDR			0x19200000
-#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SECT_SIZE + \
-						 128*1024)
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
- * 16MB StrataFlash #1 @ 0x10000000
- * 16MB StrataFlash #2 @ 0x11000000
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS		3
-#define CONFIG_SYS_FLASH_BASE			0x38000000
-#define CONFIG_SYS_FLASH_BASE_1			0x10000000
-#define CONFIG_SYS_FLASH_BASE_2			0x11000000
-#define CONFIG_SYS_FLASH_BANKS_LIST		{CONFIG_SYS_FLASH_BASE,   \
-						 CONFIG_SYS_FLASH_BASE_1, \
-						 CONFIG_SYS_FLASH_BASE_2}
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_SECT		128
-#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-#define CONFIG_SYS_FLASH_ERASE_TOUT		2000	/* ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT		2000	/* ms */
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- * - Boot flash is 512kB with 64kB sectors
- * - StrataFlash is 32MB with 128kB sectors
- * - Redundant embedded environment is 25% of the Boot flash
- * - Redundant StrataFlash environment is <1% of the StrataFlash
- * - Environment is therefore located in StrataFlash
- * - Primary copy is located in first sector of first flash
- * - Redundant copy is located in second sector of first flash
- * - Stack is only 32kB, so environment size is limited to 4kB
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE			0x20000
-#define CONFIG_ENV_SIZE				0x01000
-#define CONFIG_ENV_ADDR				CONFIG_SYS_FLASH_BASE_1
-#define CONFIG_ENV_ADDR_REDUND			(CONFIG_SYS_FLASH_BASE_1 + \
-						 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND			CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_SYS_FIRST_PCI_IRQ		10
-#define CONFIG_SYS_SECOND_PCI_IRQ		9
-#define CONFIG_SYS_THIRD_PCI_IRQ		11
-#define CONFIG_SYS_FORTH_PCI_IRQ		15
-
-/*-----------------------------------------------------------------------
- * Network device (TRL8100B) support
- */
-#define CONFIG_RTL8139
-
-/*-----------------------------------------------------------------------
- * BOOTCS Control (for AM29LV040B-120JC)
- *
- * 000 0 00 0 000 11 0 011 }- 0x0033
- * \ / | \| | \ / \| | \ /
- *  |  |  | |  |   | |  |
- *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
- *  |  |  | |  |   | +------- Reserved
- *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
- *  |  |  | |  +------------- Reserved
- *  |  |  | +---------------- Non-Paged Mode
- *  |  |  +------------------ 8 Bit Wide
- *  |  +--------------------- GP Bus
- *  +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_BOOTCS_CTRL		0x0033
-
-/*-----------------------------------------------------------------------
- * ROMCS Control (for E28F128J3A-150 StrataFlash)
- *
- * 000 0 01 1 000 01 0 101 }- 0x0615
- * \ / | \| | \ / \| | \ /
- *  |  |  | |  |   | |  |
- *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
- *  |  |  | |  |   | +------- Reserved
- *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
- *  |  |  | |  +------------- Reserved
- *  |  |  | +---------------- Paged Mode
- *  |  |  +------------------ 16 Bit Wide
- *  |  +--------------------- GP Bus
- *  +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_ROMCS1_CTRL		0x0615
-#define CONFIG_SYS_SC520_ROMCS2_CTRL		0x0615
-
-/*-----------------------------------------------------------------------
- * SC520 General Purpose Bus configuration
- *
- * Chip Select Offset		1 Clock Cycle
- * Chip Select Pulse Width	8 Clock Cycles
- * Chip Select Read Offset	2 Clock Cycles
- * Chip Select Read Width	6 Clock Cycles
- * Chip Select Write Offset	2 Clock Cycles
- * Chip Select Write Width	6 Clock Cycles
- * Chip Select Recovery Time	2 Clock Cycles
- *
- * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
- *
- *   |<-------------General Purpose Bus Cycle---------------->|
- *   |                                                        |
- * ----------------------\__________________/------------------
- *   |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
- *
- * ------------------------\_______________/-------------------
- *   |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
- *
- * --------------------------\_______________/-----------------
- *   |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
- *
- * ________/-----------\_______________________________________
- *   |<--->|<--------->|
- *      ^         ^
- * (GPALEOFF + 1) |
- *                |
- *         (GPALEW + 1)
- */
-#define CONFIG_SYS_SC520_GPCSOFF		0x00
-#define CONFIG_SYS_SC520_GPCSPW			0x07
-#define CONFIG_SYS_SC520_GPRDOFF		0x01
-#define CONFIG_SYS_SC520_GPRDW			0x05
-#define CONFIG_SYS_SC520_GPWROFF		0x01
-#define CONFIG_SYS_SC520_GPWRW			0x05
-#define CONFIG_SYS_SC520_GPCSRT			0x01
-
-/*-----------------------------------------------------------------------
- * SC520 Programmable I/O configuration
- *
- * Pin	  Mode		Dir.	Description
- * ----------------------------------------------------------------------
- * PIO0   PIO		Output	Unused
- * PIO1   GPBHE#	Output	GP Bus Byte High Enable (active low)
- * PIO2   PIO		Output	Auxiliary power output enable
- * PIO3   GPAEN		Output	GP Bus Address Enable
- * PIO4   PIO		Output	Top Board Enable (active low)
- * PIO5   PIO		Output	StrataFlash 16 bit mode (low = 8 bit mode)
- * PIO6   PIO		Input	Data output of Power Supply ADC
- * PIO7   PIO		Output	Clock input to Power Supply ADC
- * PIO8   PIO		Output  Chip Select input of Power Supply ADC
- * PIO9   PIO		Output	StrataFlash 1 Reset / Power Down (active low)
- * PIO10  PIO		Output	StrataFlash 2 Reset / Power Down (active low)
- * PIO11  PIO		Input	StrataFlash 1 Status
- * PIO12  PIO		Input	StrataFlash 2 Status
- * PIO13  GPIRQ10#	Input	Can Bus / I2C IRQ (active low)
- * PIO14  PIO		Input	Low Input Voltage Warning (active low)
- * PIO15  PIO		Output	Watchdog (must toggle at least every 1.6s)
- * PIO16  PIO		Input	Power Fail
- * PIO17  GPIRQ6	Input	Compact Flash 1 IRQ (active low)
- * PIO18  GPIRQ5	Input	Compact Flash 2 IRQ (active low)
- * PIO19  GPIRQ4#	Input	Dual-Port RAM IRQ (active low)
- * PIO20  GPIRQ3	Input	UART D IRQ
- * PIO21  GPIRQ2	Input	UART C IRQ
- * PIO22  GPIRQ1	Input	UART B IRQ
- * PIO23  GPIRQ0	Input	UART A IRQ
- * PIO24  GPDBUFOE#	Output	GP Bus Data Bus Buffer Output Enable
- * PIO25  PIO		Input	Battery OK Indication
- * PIO26  GPMEMCS16#	Input	GP Bus Memory Chip-Select 16-bit access
- * PIO27  GPCS0#	Output	SRAM 1 Chip Select
- * PIO28  PIO		Input	Top Board UART CTS
- * PIO29  PIO		Output	FPGA Program Mode (active low)
- * PIO30  PIO		Input	FPGA Initialised (active low)
- * PIO31  PIO		Input	FPGA Done (active low)
- */
-#define CONFIG_SYS_SC520_PIOPFS15_0		0x200a
-#define CONFIG_SYS_SC520_PIOPFS31_16		0x0dfe
-#define CONFIG_SYS_SC520_PIODIR15_0		0x87bf
-#define CONFIG_SYS_SC520_PIODIR31_16		0x2900
-
-/*-----------------------------------------------------------------------
- * PIO Pin defines
- */
-#define CONFIG_SYS_ENET_AUX_PWR			0x0004
-#define CONFIG_SYS_ENET_TOP_BRD_PWR		0x0010
-#define CONFIG_SYS_ENET_SF_WIDTH		0x0020
-#define CONFIG_SYS_ENET_PWR_ADC_DATA		0x0040
-#define CONFIG_SYS_ENET_PWR_ADC_CLK		0x0080
-#define CONFIG_SYS_ENET_PWR_ADC_CS		0x0100
-#define CONFIG_SYS_ENET_SF1_MODE		0x0200
-#define CONFIG_SYS_ENET_SF2_MODE		0x0400
-#define CONFIG_SYS_ENET_SF1_STATUS		0x0800
-#define CONFIG_SYS_ENET_SF2_STATUS		0x1000
-#define CONFIG_SYS_ENET_PWR_STATUS		0x4000
-#define CONFIG_SYS_ENET_WATCHDOG		0x8000
-
-#define CONFIG_SYS_ENET_PWR_FAIL		0x0001
-#define CONFIG_SYS_ENET_BAT_OK			0x0200
-#define CONFIG_SYS_ENET_TOP_BRD_CTS		0x1000
-#define CONFIG_SYS_ENET_FPGA_PROG		0x2000
-#define CONFIG_SYS_ENET_FPGA_INIT		0x4000
-#define CONFIG_SYS_ENET_FPGA_DONE		0x8000
-
-/*-----------------------------------------------------------------------
- * Chip Select Pin Function Select
- *
- * 1 1 1 1 1 0 0 0 }- 0xf8
- * | | | | | | | |
- * | | | | | | | +--- Reserved
- * | | | | | | +----- GPCS1_SEL = ROMCS1#
- * | | | | | +------- GPCS2_SEL = ROMCS2#
- * | | | | +--------- GPCS3_SEL = GPCS3
- * | | | +----------- GPCS4_SEL = GPCS4
- * | | +------------- GPCS5_SEL = GPCS5
- * | +--------------- GPCS6_SEL = GPCS6
- * +----------------- GPCS7_SEL = GPCS7
- */
-#define CONFIG_SYS_SC520_CSPFS			0xf8
-
-/*-----------------------------------------------------------------------
- * Clock Select (CLKTIMER[CLKTEST] pin)
- *
- * 0 111 00 1 0 }- 0x72
- * | \ / \| | |
- * |  |   | | +--- Pin Disabled
- * |  |   | +----- Pin is an output
- * |  |   +------- Reserved
- * |  +----------- Disabled (pin stays Low)
- * +-------------- Reserved
- */
-#define CONFIG_SYS_SC520_CLKSEL			0x72
-
-/*-----------------------------------------------------------------------
- * Address Decode Control
- *
- * 0 00 0 0 0 0 0 }- 0x00
- * | \| | | | | |
- * |  | | | | | +--- Integrated UART 1 is enabled
- * |  | | | | +----- Integrated UART 2 is enabled
- * |  | | | +------- Integrated RTC is enabled
- * |  | | +--------- Reserved
- * |  | +----------- I/O Hole accesses are forwarded to the external GP bus
- * |  +------------- Reserved
- * +---------------- Write-protect violations do not generate an IRQ
- */
-#define CONFIG_SYS_SC520_ADDDECCTL		0x00
-
-/*-----------------------------------------------------------------------
- * UART Control
- *
- * 00000 1 1 1 }- 0x07
- * \___/ | | |
- *   |   | | +--- Transmit TC interrupt enable
- *   |   | +----- Receive TC interrupt enable
- *   |   +------- 1.8432 MHz
- *   +----------- Reserved
- */
-#define CONFIG_SYS_SC520_UART1CTL		0x07
-#define CONFIG_SYS_SC520_UART2CTL		0x07
-
-/*-----------------------------------------------------------------------
- * System Arbiter Control
- *
- * 00000 1 1 0 }- 0x06
- * \___/ | | |
- *   |   | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
- *   |   | +----- The system arbiter operates in concurrent mode
- *   |   +------- Park the PCI bus on the last master that acquired the bus
- *   +----------- Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBCTL		0x06
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 00000000000 0 0 0 1 1 }- 0x06
- * \_________/ | | | | |
- *      |      | | | | +--- PCI master REQ0 enabled (Ethernet 1)
- *      |      | | | +----- PCI master REQ1 enabled (Ethernet 2)
- *      |      | | +------- PCI master REQ2 disabled
- *      |      | +--------- PCI master REQ3 disabled
- *      |      +----------- PCI master REQ4 disabled
- *      +------------------ Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBMENB		0x0003
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 0 0000 0 00 0000 1 000 }- 0x06
- * | \__/ | \| \__/ | \_/
- * |   |  |  |   |  |  +---- Reserved
- * |   |  |  |   |  +------- Enable CPU-to-PCI bus write posting
- * |   |  |  |   +---------- Reserved
- * |   |  |  +-------------- PCI bus reads to SDRAM are not automatically
- * |   |  |                  retried
- * |   |  +----------------- Target read FIFOs are not snooped during write
- * |   |                     transactions
- * |   +-------------------- Reserved
- * +------------------------ Deassert the PCI bus reset signal
- */
-#define CONFIG_SYS_SC520_HBCTL			0x08
-
-/*-----------------------------------------------------------------------
- * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
- * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
- * \ / | | | | \----+----/ \-----+------/
- *  |  | | | |      |            +---------- Start at 0x38000000
- *  |  | | | |      +----------------------- 512kB Region Size
- *  |  | | | |                               ((7 + 1) * 64kB)
- *  |  | | | +------------------------------ 64kB Page Size
- *  |  | | +-------------------------------- Writes Enabled (So it can be
- *  |  | |                                   reprogrammed!)
- *  |  | +---------------------------------- Caching Disabled
- *  |  +------------------------------------ Execution Enabled
- *  +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_BOOTCS_PAR		0x8a01f800
-
-/*-----------------------------------------------------------------------
- * Cache-As-RAM (Targets Boot Flash)
- *
- * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
- * \ / | | | | \--+--/ \-------+--------/
- *  |  | | | |    |            +------------ Start at 0x19200000
- *  |  | | | |    +------------------------- 64k Region Size
- *  |  | | | |                               ((15 + 1) * 4kB)
- *  |  | | | +------------------------------ 4kB Page Size
- *  |  | | +-------------------------------- Writes Enabled
- *  |  | +---------------------------------- Caching Enabled
- *  |  +------------------------------------ Execution Prevented
- *  +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_CAR_PAR		0x903d9200
-
-/*-----------------------------------------------------------------------
- * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
- *
- * 001 110 0 000100000 0001000000000000 }- 0x38201000
- * \ / \ / | \---+---/ \------+-------/
- *  |   |  |     |            +----------- Start at 0x00001000
- *  |   |  |     +------------------------ 33 Bytes (0x20 + 1)
- *  |   |  +------------------------------ Ignored
- *  |   +--------------------------------- GPCS6
- *  +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_LLIO_PAR		0x38201000
-
-/*-----------------------------------------------------------------------
- * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
- * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
- *
- * 010 101 0 0000000 100000000000000000 }- 0x54020000
- * 010 111 0 0000000 100000000000000001 }- 0x5c020001
- * \ / \ / | \--+--/ \-------+--------/
- *  |   |  |    |            +------------ Start at 0x200000000
- *  |   |  |    |                                   0x200010000
- *  |   |  |    +------------------------- 4kB Region Size
- *  |   |  |                               ((0 + 1) * 4kB)
- *  |   |  +------------------------------ 4k Page Size
- *  |   +--------------------------------- GPCS5
- *  |                                      GPCS7
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_CF1_PAR		0x54020000
-#define CONFIG_SYS_SC520_CF2_PAR		0x5c020001
-
-/*-----------------------------------------------------------------------
- * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
- * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
- * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
- * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
- *
- * 001 000 0 000000111 0001001111111000 }- 0x200713f8
- * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
- * 001 011 0 000000111 0001001011111000 }- 0x300711f8
- * 001 011 0 000000111 0001001011111000 }- 0x340710f8
- * \ / \ / | \---+---/ \------+-------/
- *  |   |  |     |            +----------- Start at 0x013f8
- *  |   |  |     |                                  0x012f8
- *  |   |  |     |                                  0x011f8
- *  |   |  |     |                                  0x010f8
- *  |   |  |     +------------------------ 33 Bytes (32 + 1)
- *  |   |  +------------------------------ Ignored
- *  |   +--------------------------------- GPCS6
- *  +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_UARTA_PAR		0x200713f8
-#define CONFIG_SYS_SC520_UARTB_PAR		0x2c0712f8
-#define CONFIG_SYS_SC520_UARTC_PAR		0x300711f8
-#define CONFIG_SYS_SC520_UARTD_PAR		0x340710f8
-
-/*-----------------------------------------------------------------------
- * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
- * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
- *
- * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
- * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
- * \ / | | | | \----+----/ \-----+------/
- *  |  | | | |      |            +---------- Start at 0x10000000
- *  |  | | | |      |                                 0x11000000
- *  |  | | | |      +----------------------- 16MB Region Size
- *  |  | | | |                               ((255 + 1) * 64kB)
- *  |  | | | +------------------------------ 64kB Page Size
- *  |  | | +-------------------------------- Writes Enabled
- *  |  | +---------------------------------- Caching Disabled
- *  |  +------------------------------------ Execution Enabled
- *  +--------------------------------------- ROMCS1
- *                                           ROMCS2
- */
-#define CONFIG_SYS_SC520_SF1_PAR		0xaa3fd000
-#define CONFIG_SYS_SC520_SF2_PAR		0xca3fd100
-
-/*-----------------------------------------------------------------------
- * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
- * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
- *
- * 010 000 1 00000001111 01100100000000 }- 0x4203d900
- * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
- * \ / \ / | \----+----/ \-----+------/
- *  |   |  |      |            +---------- Start at 0x19000000
- *  |   |  |      |                                 0x19100000
- *  |   |  |      +----------------------- 1MB Region Size
- *  |   |  |                               ((15 + 1) * 64kB)
- *  |   |  +------------------------------ 64kB Page Size
- *  |   +--------------------------------- GPCS0
- *  |                                      GPCS3
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_SRAM1_PAR		0x4203d900
-#define CONFIG_SYS_SC520_SRAM2_PAR		0x4e03d910
-
-/*-----------------------------------------------------------------------
- * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
- *
- * 010 100 0 00000000 11000000100000000 }- 0x50018100
- * \ / \ / | \---+--/ \-------+-------/
- *  |   |  |     |            +----------- Start at 0x18100000
- *  |   |  |     +------------------------ 4kB Region Size
- *  |   |  |                               ((0 + 1) * 4kB)
- *  |   |  +------------------------------ 4kB Page Size
- *  |   +--------------------------------- GPCS4
- *  +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_DPRAM_PAR		0x50018100
-
-#endif	/* __CONFIG_H */