From patchwork Thu Feb 14 12:56:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Diana Craciun X-Patchwork-Id: 220436 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 071C22C03A7 for ; Thu, 14 Feb 2013 23:57:21 +1100 (EST) Received: by ozlabs.org (Postfix) id C7EF92C007C; Thu, 14 Feb 2013 23:56:54 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from db3outboundpool.messaging.microsoft.com (db3ehsobe001.messaging.microsoft.com [213.199.154.139]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 170202C0077 for ; Thu, 14 Feb 2013 23:56:53 +1100 (EST) Received: from mail79-db3-R.bigfish.com (10.3.81.225) by DB3EHSOBE008.bigfish.com (10.3.84.28) with Microsoft SMTP Server id 14.1.225.23; Thu, 14 Feb 2013 12:56:49 +0000 Received: from mail79-db3 (localhost [127.0.0.1]) by mail79-db3-R.bigfish.com (Postfix) with ESMTP id 83A7912028A for ; Thu, 14 Feb 2013 12:56:49 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1155h) Received: from mail79-db3 (localhost.localdomain [127.0.0.1]) by mail79-db3 (MessageSwitch) id 1360846608271040_10672; Thu, 14 Feb 2013 12:56:48 +0000 (UTC) Received: from DB3EHSMHS009.bigfish.com (unknown [10.3.81.232]) by mail79-db3.bigfish.com (Postfix) with ESMTP id 4027630004B for ; Thu, 14 Feb 2013 12:56:48 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS009.bigfish.com (10.3.87.109) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 14 Feb 2013 12:56:41 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 14 Feb 2013 12:56:39 +0000 Received: from zro04-ws660.ea.freescale.net (zro04-ws660.ea.freescale.net [10.171.73.85]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r1ECuc2g029137; Thu, 14 Feb 2013 05:56:38 -0700 From: Diana Craciun To: Subject: [PATCH][RFC] Replaced tlbilx with tlbwe in the initialization code Date: Thu, 14 Feb 2013 14:56:35 +0200 Message-ID: <1360846595-3397-1-git-send-email-diana.craciun@freescale.com> X-Mailer: git-send-email 1.7.11.7 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Diana Craciun X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Diana Craciun On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Linux is using tlbilx in the boot code to invalidate the temporary entries it creates when initializing the MMU. The patch is replacing the usage of tlbilx in initialization code with tlbwe with VALID bit cleared. Linux is also using tlbilx in other contexts (like huge pages or indirect entries) but removing the tlbilx from the initialization code offers the possibility to have scenarios under hypervisor which are not using huge pages or indirect entries. Signed-off-by: Diana Craciun --- arch/powerpc/kernel/exceptions-64e.S | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 4684e33..1f0ae33 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -1010,12 +1010,9 @@ skpinv: addi r6,r6,1 /* Increment */ mtspr SPRN_MAS0,r3 tlbre mfspr r6,SPRN_MAS1 - rlwinm r6,r6,0,2,0 /* clear IPROT */ + rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ mtspr SPRN_MAS1,r6 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync @@ -1069,12 +1066,9 @@ skpinv: addi r6,r6,1 /* Increment */ mtspr SPRN_MAS0,r4 tlbre mfspr r5,SPRN_MAS1 - rlwinm r5,r5,0,2,0 /* clear IPROT */ + rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ mtspr SPRN_MAS1,r5 tlbwe - - /* Invalidate TLB1 */ - PPC_TLBILX_ALL(0,R0) sync isync