From patchwork Wed Feb 13 14:43:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 220154 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CB37B2C0293 for ; Thu, 14 Feb 2013 01:49:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E54D4A1B0; Wed, 13 Feb 2013 15:49:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m0zD0CookvOM; Wed, 13 Feb 2013 15:49:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6409D4A1A3; Wed, 13 Feb 2013 15:49:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 01F644A1A3 for ; Wed, 13 Feb 2013 15:49:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9DvN3jyjF97h for ; Wed, 13 Feb 2013 15:49:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ia0-f169.google.com (mail-ia0-f169.google.com [209.85.210.169]) by theia.denx.de (Postfix) with ESMTPS id 683A74A199 for ; Wed, 13 Feb 2013 15:49:48 +0100 (CET) Received: by mail-ia0-f169.google.com with SMTP id j5so1280641iaf.28 for ; Wed, 13 Feb 2013 06:49:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=yF+Zhf95/xz+JTrnH6mQL8OAzyKaPUSSl54BbXZ7tjY=; b=LqLp/vCyKb2aB8FVFKRqAkCZUsxIEgsG253OO9AxRzmrhburKXgeJttPSQdgV7Fehx cgwsQclVzWH0QjFAKISEjGjxhEJofUIMcg0MHUWydkx0RyOk1PqXu6+nfjSAVokb8/6N Lo9dhzYMucNi+8CA+8IQ19PLcZil+bBpk+xJJPFIhqQP5ZMR8Juv8RQEpxJ+N6n9/+i3 J+7TI1XZZGsXXke6NiQy2V+a9lkk52dhcuWO/ildXMARkkltUC/ZoNL9D1QnJnbSoVFg X1vqSOPAFxNd4FERb1GOpqWwEm2PquZTgQVAw3rw8m3ATx59mireYqv9s2aKnuQcHIY6 vW9w== X-Received: by 10.50.149.233 with SMTP id ud9mr11484784igb.92.1360766577202; Wed, 13 Feb 2013 06:42:57 -0800 (PST) Received: from beef.ohporter.com (cpe-24-166-64-7.neo.res.rr.com. [24.166.64.7]) by mx.google.com with ESMTPS id j11sm40254965igc.5.2013.02.13.06.42.56 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Feb 2013 06:42:56 -0800 (PST) From: Matt Porter To: U-Boot Mailing List Date: Wed, 13 Feb 2013 09:43:59 -0500 Message-Id: <1360766644-9901-6-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360766644-9901-1-git-send-email-mporter@ti.com> References: <1360766644-9901-1-git-send-email-mporter@ti.com> Cc: Tom Rini Subject: [U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Support the ti814x specific register definitions within arch-am33xx. Signed-off-by: Matt Porter Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/sys_info.c | 3 +++ arch/arm/include/asm/arch-am33xx/cpu.h | 11 +++++---- arch/arm/include/asm/arch-am33xx/hardware.h | 32 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/omap.h | 7 ++++++ arch/arm/include/asm/arch-am33xx/spl.h | 5 +++++ 5 files changed, 54 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 507b618..402127c 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -98,6 +98,9 @@ int print_cpuinfo(void) case AM335X: cpu_s = "AM335X"; break; + case TI81XX: + cpu_s = "TI81XX"; + break; default: cpu_s = "Unknown cpu type"; break; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 16e8a80..3d3a7c8 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -42,9 +42,10 @@ #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 -/* cpu-id for AM33XX family */ +/* cpu-id for AM33XX and TI81XX family */ #define AM335X 0xB944 -#define DEVICE_ID 0x44E10600 +#define TI81XX 0xB81E +#define DEVICE_ID (CTRL_BASE + 0x0600) /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ @@ -52,9 +53,11 @@ /* Reset control */ #ifdef CONFIG_AM33XX -#define PRM_RSTCTRL 0x44E00F00 -#define PRM_RSTST 0x44E00F08 +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#elif defined(CONFIG_TI814X) +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #endif +#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 41ab2c0..786c159 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -20,9 +20,14 @@ #define __AM33XX_HARDWARE_H #include +#include /* Module base addresses */ +#ifdef CONFIG_AM33XX #define UART0_BASE 0x44E09000 +#elif defined(CONFIG_TI814X) +#define UART0_BASE 0x48020000 +#endif /* DM Timer base addresses */ #define DM_TIMER0_BASE 0x4802C000 @@ -37,20 +42,39 @@ /* GPIO Base address */ #define GPIO0_BASE 0x48032000 #define GPIO1_BASE 0x4804C000 +#ifdef CONFIG_AM33XX #define GPIO2_BASE 0x481AC000 +#endif /* BCH Error Location Module */ #define ELM_BASE 0x48080000 /* Watchdog Timer */ +#ifdef CONFIG_AM33XX #define WDT_BASE 0x44E35000 +#elif defined(CONFIG_TI814X) +#define WDT_BASE 0x481C7000 +#endif /* Control Module Base Address */ +#ifdef CONFIG_AM33XX #define CTRL_BASE 0x44E10000 #define CTRL_DEVICE_BASE 0x44E10600 +#elif defined(CONFIG_TI814X) +#define CTRL_BASE 0x48140000 +#endif /* PRCM Base Address */ +#ifdef CONFIG_AM33XX #define PRCM_BASE 0x44E00000 +#elif defined(CONFIG_TI814X) +#define PRCM_BASE 0x48180000 +#endif + +/* PLL Subsystem Base Address */ +#ifdef CONFIG_TI814X +#define PLL_SUBSYS_BASE 0x481C5000 +#endif /* EMIF Base address */ #define EMIF4_0_CFG_BASE 0x4C000000 @@ -99,10 +123,18 @@ /* CPSW Config space */ #define CPSW_BASE 0x4A100000 +#ifdef CONFIG_AM33XX #define CPSW_MDIO_BASE 0x4A101000 +#elif defined(CONFIG_TI814X) +#define CPSW_MDIO_BASE 0x4A100800 +#endif /* RTC base address */ +#ifdef CONFIG_AM33XX #define RTC_BASE 0x44E3E000 +#elif defined(CONFIG_TI814X) +#define RTC_BASE 0x480C0000 +#endif /* OTG */ #define USB0_OTG_BASE 0x47401000 diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 850f8a5..ba4f6d2 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -23,13 +23,20 @@ #ifndef _OMAP_H_ #define _OMAP_H_ +#include + /* * Non-secure SRAM Addresses * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ +#ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 +#elif defined(CONFIG_TI814X) +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 +#endif /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 644ff35..9b5fe9e 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -25,8 +25,13 @@ #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 +#ifdef CONFIG_AM33XX #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ +#elif defined(CONFIG_TI814X) +#define BOOT_DEVICE_MMC1 9 +#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */ +#endif #define BOOT_DEVICE_SPI 11 #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_CPGMAC 70