Patchwork [U-Boot,2/7] arm: dra7xx: clock: Add the prcm changes

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Submitter Lokesh Vutla
Date Feb. 13, 2013, 7:29 a.m.
Message ID <1360740549-32588-3-git-send-email-lokeshvutla@ti.com>
Download mbox | patch
Permalink /patch/220066/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Lokesh Vutla - Feb. 13, 2013, 7:29 a.m.
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
 arch/arm/cpu/armv7/omap4/hw_data.c     |    2 +-
 arch/arm/cpu/armv7/omap4/prcm-regs.c   |    2 +-
 arch/arm/cpu/armv7/omap5/hw_data.c     |    6 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |  218 +++++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-omap5/cpu.h  |    4 +
 arch/arm/include/asm/arch-omap5/omap.h |    9 +-
 arch/arm/include/asm/omap_common.h     |   15 ++-
 7 files changed, 249 insertions(+), 7 deletions(-)
Tom Rini - Feb. 15, 2013, 4:34 p.m.
On Wed, Feb 13, 2013 at 12:59:04PM +0530, Lokesh Vutla wrote:

> PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
> So adding the necessary register changes for DRA7XX socs.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: R Sricharan <r.sricharan@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

Patch

diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 8d31d6d..3b27bc1 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -290,7 +290,7 @@  void enable_basic_clocks(void)
 	};
 
 	u32 const clk_modules_hw_auto_essential[] = {
-		(*prcm)->cm_l3_2_gpmc_clkctrl,
+		(*prcm)->cm_l3_gpmc_clkctrl,
 		(*prcm)->cm_memif_emif_1_clkctrl,
 		(*prcm)->cm_memif_emif_2_clkctrl,
 		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index c58ce8d..7225a30 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -153,7 +153,7 @@  struct prcm_regs const omap4_prcm = {
 	.cm_l3_2_clkstctrl = 0x4a008800,
 	.cm_l3_2_dynamicdep = 0x4a008808,
 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
-	.cm_l3_2_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
 	.cm_mpu_m3_clkstctrl = 0x4a008900,
 	.cm_mpu_m3_staticdep = 0x4a008904,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1701b09..22590f4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -278,7 +278,7 @@  void enable_basic_clocks(void)
 	};
 
 	u32 const clk_modules_hw_auto_essential[] = {
-		(*prcm)->cm_l3_2_gpmc_clkctrl,
+		(*prcm)->cm_l3_gpmc_clkctrl,
 		(*prcm)->cm_memif_emif_1_clkctrl,
 		(*prcm)->cm_memif_emif_2_clkctrl,
 		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
@@ -503,6 +503,10 @@  void hw_data_init(void)
 	*omap_vcores = &omap5430_volts_es2;
 	break;
 
+	case DRA752_ES1_0:
+	*prcm = &dra7xx_prcm;
+	break;
+
 	default:
 		printf("\n INVALID OMAP REVISION ");
 	}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5e5abcc..c8f62d1 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -156,7 +156,7 @@  struct prcm_regs const omap5_es1_prcm = {
 	.cm_l3_2_clkstctrl = 0x4a008800,
 	.cm_l3_2_dynamicdep = 0x4a008808,
 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
-	.cm_l3_2_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
 	.cm_mpu_m3_clkstctrl = 0x4a008900,
 	.cm_mpu_m3_staticdep = 0x4a008904,
@@ -513,7 +513,7 @@  struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3_2_clkstctrl = 0x4a008800,
 	.cm_l3_2_dynamicdep = 0x4a008808,
 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
-	.cm_l3_2_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
 	.cm_mpu_m3_clkstctrl = 0x4a008900,
 	.cm_mpu_m3_staticdep = 0x4a008904,
@@ -664,3 +664,217 @@  struct prcm_regs const omap5_es2_prcm = {
 	.prm_sldo_mm_setup = 0x4ae07cd4,
 	.prm_sldo_mm_ctrl = 0x4ae07cd8,
 };
+
+struct prcm_regs const dra7xx_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core				= 0x4a005100,
+	.cm_clksel_abe				= 0x4a005108,
+	.cm_dll_ctrl				= 0x4a005110,
+	.cm_clkmode_dpll_core			= 0x4a005120,
+	.cm_idlest_dpll_core			= 0x4a005124,
+	.cm_autoidle_dpll_core			= 0x4a005128,
+	.cm_clksel_dpll_core			= 0x4a00512c,
+	.cm_div_m2_dpll_core			= 0x4a005130,
+	.cm_div_m3_dpll_core			= 0x4a005134,
+	.cm_div_h11_dpll_core			= 0x4a005138,
+	.cm_div_h12_dpll_core			= 0x4a00513c,
+	.cm_div_h13_dpll_core			= 0x4a005140,
+	.cm_div_h14_dpll_core			= 0x4a005144,
+	.cm_ssc_deltamstep_dpll_core		= 0x4a005148,
+	.cm_ssc_modfreqdiv_dpll_core		= 0x4a00514c,
+	.cm_div_h21_dpll_core			= 0x4a005150,
+	.cm_div_h22_dpllcore			= 0x4a005154,
+	.cm_div_h23_dpll_core			= 0x4a005158,
+	.cm_div_h24_dpll_core			= 0x4a00515c,
+	.cm_clkmode_dpll_mpu			= 0x4a005160,
+	.cm_idlest_dpll_mpu			= 0x4a005164,
+	.cm_autoidle_dpll_mpu			= 0x4a005168,
+	.cm_clksel_dpll_mpu			= 0x4a00516c,
+	.cm_div_m2_dpll_mpu			= 0x4a005170,
+	.cm_ssc_deltamstep_dpll_mpu		= 0x4a005188,
+	.cm_ssc_modfreqdiv_dpll_mpu		= 0x4a00518c,
+	.cm_bypclk_dpll_mpu			= 0x4a00519c,
+	.cm_clkmode_dpll_iva			= 0x4a0051a0,
+	.cm_idlest_dpll_iva			= 0x4a0051a4,
+	.cm_autoidle_dpll_iva			= 0x4a0051a8,
+	.cm_clksel_dpll_iva			= 0x4a0051ac,
+	.cm_ssc_deltamstep_dpll_iva		= 0x4a0051c8,
+	.cm_ssc_modfreqdiv_dpll_iva		= 0x4a0051cc,
+	.cm_bypclk_dpll_iva			= 0x4a0051dc,
+	.cm_clkmode_dpll_abe			= 0x4a0051e0,
+	.cm_idlest_dpll_abe			= 0x4a0051e4,
+	.cm_autoidle_dpll_abe			= 0x4a0051e8,
+	.cm_clksel_dpll_abe			= 0x4a0051ec,
+	.cm_div_m2_dpll_abe			= 0x4a0051f0,
+	.cm_div_m3_dpll_abe			= 0x4a0051f4,
+	.cm_ssc_deltamstep_dpll_abe		= 0x4a005208,
+	.cm_ssc_modfreqdiv_dpll_abe		= 0x4a00520c,
+	.cm_clkmode_dpll_ddrphy			= 0x4a005210,
+	.cm_idlest_dpll_ddrphy			= 0x4a005214,
+	.cm_autoidle_dpll_ddrphy		= 0x4a005218,
+	.cm_clksel_dpll_ddrphy			= 0x4a00521c,
+	.cm_div_m2_dpll_ddrphy			= 0x4a005220,
+	.cm_div_h11_dpll_ddrphy			= 0x4a005228,
+	.cm_ssc_deltamstep_dpll_ddrphy		= 0x4a00522c,
+	.cm_clkmode_dpll_dsp			= 0x4a005234,
+	.cm_shadow_freq_config1			= 0x4a005260,
+
+	/* cm1.mpu */
+	.cm_mpu_mpu_clkctrl			= 0x4a005320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl			= 0x4a005400,
+	.cm_dsp_dsp_clkctrl			= 0x4a005420,
+
+	/* cm2.ckgen */
+	.cm_clksel_usb_60mhz			= 0x4a008104,
+	.cm_clkmode_dpll_per			= 0x4a008140,
+	.cm_idlest_dpll_per			= 0x4a008144,
+	.cm_autoidle_dpll_per			= 0x4a008148,
+	.cm_clksel_dpll_per			= 0x4a00814c,
+	.cm_div_m2_dpll_per			= 0x4a008150,
+	.cm_div_m3_dpll_per			= 0x4a008154,
+	.cm_div_h11_dpll_per			= 0x4a008158,
+	.cm_div_h12_dpll_per			= 0x4a00815c,
+	.cm_div_h13_dpll_per			= 0x4a008160,
+	.cm_div_h14_dpll_per			= 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per		= 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per		= 0x4a00816c,
+	.cm_clkmode_dpll_usb			= 0x4a008180,
+	.cm_idlest_dpll_usb			= 0x4a008184,
+	.cm_autoidle_dpll_usb			= 0x4a008188,
+	.cm_clksel_dpll_usb			= 0x4a00818c,
+	.cm_div_m2_dpll_usb			= 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb		= 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb		= 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb			= 0x4a0081b4,
+	.cm_clkmode_dpll_pcie_ref		= 0x4a008200,
+	.cm_clkmode_apll_pcie			= 0x4a00821c,
+	.cm_idlest_apll_pcie			= 0x4a008220,
+	.cm_div_m2_apll_pcie			= 0x4a008224,
+	.cm_clkvcoldo_apll_pcie			= 0x4a008228,
+
+	/* cm2.core */
+	.cm_l3_1_clkstctrl			= 0x4a008700,
+	.cm_l3_1_dynamicdep			= 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl			= 0x4a008720,
+	.cm_l3_gpmc_clkctrl			= 0x4a008728,
+	.cm_mpu_m3_clkstctrl			= 0x4a008900,
+	.cm_mpu_m3_staticdep			= 0x4a008904,
+	.cm_mpu_m3_dynamicdep			= 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl		= 0x4a008920,
+	.cm_sdma_clkstctrl			= 0x4a008a00,
+	.cm_sdma_staticdep			= 0x4a008a04,
+	.cm_sdma_dynamicdep			= 0x4a008a08,
+	.cm_sdma_sdma_clkctrl			= 0x4a008a20,
+	.cm_memif_clkstctrl			= 0x4a008b00,
+	.cm_memif_dmm_clkctrl			= 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl		= 0x4a008b28,
+	.cm_memif_emif_1_clkctrl		= 0x4a008b30,
+	.cm_memif_emif_2_clkctrl		= 0x4a008b38,
+	.cm_memif_dll_clkctrl			= 0x4a008b40,
+	.cm_l4cfg_clkstctrl			= 0x4a008d00,
+	.cm_l4cfg_dynamicdep			= 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl		= 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl		= 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl		= 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl		= 0x4a008d38,
+	.cm_l3instr_clkstctrl			= 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl		= 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl		= 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkctrl	= 0x4a008e40,
+
+	/* cm2.ivahd */
+	.cm_ivahd_clkstctrl			= 0x4a008f00,
+	.cm_ivahd_ivahd_clkctrl			= 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl			= 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl			= 0x4a009000,
+	.cm_cam_vip1_clkctrl			= 0x4a009020,
+	.cm_cam_vip2_clkctrl			= 0x4a009028,
+	.cm_cam_vip3_clkctrl			= 0x4a009030,
+	.cm_cam_lvdsrx_clkctrl			= 0x4a009038,
+	.cm_cam_csi1_clkctrl			= 0x4a009040,
+	.cm_cam_csi2_clkctrl			= 0x4a009048,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl			= 0x4a009100,
+	.cm_dss_dss_clkctrl			= 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl			= 0x4a009200,
+	.cm_sgx_sgx_clkctrl			= 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl			= 0x4a009300,
+
+	/* cm2.l3init */
+	.cm_l3init_hsmmc1_clkctrl		= 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl		= 0x4a009330,
+	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
+	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
+	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl			= 0x4a009700,
+	.cm_l4per_dynamicdep			= 0x4a009708,
+	.cm_l4per_gptimer10_clkctrl		= 0x4a009728,
+	.cm_l4per_gptimer11_clkctrl		= 0x4a009730,
+	.cm_l4per_gptimer2_clkctrl		= 0x4a009738,
+	.cm_l4per_gptimer3_clkctrl		= 0x4a009740,
+	.cm_l4per_gptimer4_clkctrl		= 0x4a009748,
+	.cm_l4per_gptimer9_clkctrl		= 0x4a009750,
+	.cm_l4per_elm_clkctrl			= 0x4a009758,
+	.cm_l4per_gpio2_clkctrl			= 0x4a009760,
+	.cm_l4per_gpio3_clkctrl			= 0x4a009768,
+	.cm_l4per_gpio4_clkctrl			= 0x4a009770,
+	.cm_l4per_gpio5_clkctrl			= 0x4a009778,
+	.cm_l4per_gpio6_clkctrl			= 0x4a009780,
+	.cm_l4per_hdq1w_clkctrl			= 0x4a009788,
+	.cm_l4per_i2c1_clkctrl			= 0x4a0097a0,
+	.cm_l4per_i2c2_clkctrl			= 0x4a0097a8,
+	.cm_l4per_i2c3_clkctrl			= 0x4a0097b0,
+	.cm_l4per_i2c4_clkctrl			= 0x4a0097b8,
+	.cm_l4per_l4per_clkctrl			= 0x4a0097c0,
+	.cm_l4per_mcspi1_clkctrl		= 0x4a0097f0,
+	.cm_l4per_mcspi2_clkctrl		= 0x4a0097f8,
+	.cm_l4per_mcspi3_clkctrl		= 0x4a009800,
+	.cm_l4per_mcspi4_clkctrl		= 0x4a009808,
+	.cm_l4per_gpio7_clkctrl			= 0x4a009810,
+	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
+	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
+	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_uart1_clkctrl			= 0x4a009840,
+	.cm_l4per_uart2_clkctrl			= 0x4a009848,
+	.cm_l4per_uart3_clkctrl			= 0x4a009850,
+	.cm_l4per_uart4_clkctrl			= 0x4a009858,
+	.cm_l4per_uart5_clkctrl			= 0x4a009870,
+	.cm_l4sec_clkstctrl			= 0x4a009880,
+	.cm_l4sec_staticdep			= 0x4a009884,
+	.cm_l4sec_dynamicdep			= 0x4a009888,
+	.cm_l4sec_aes1_clkctrl			= 0x4a0098a0,
+	.cm_l4sec_aes2_clkctrl			= 0x4a0098a8,
+	.cm_l4sec_des3des_clkctrl		= 0x4a0098b0,
+	.cm_l4sec_rng_clkctrl			= 0x4a0098c0,
+	.cm_l4sec_sha2md51_clkctrl		= 0x4a0098c8,
+	.cm_l4sec_cryptodma_clkctrl		= 0x4a0098d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel			= 0x4ae0610c,
+	.cm_sys_clksel				= 0x4ae06110,
+	.cm_wkup_clkstctrl			= 0x4ae07800,
+	.cm_wkup_l4wkup_clkctrl			= 0x4ae07820,
+	.cm_wkup_wdtimer1_clkctrl		= 0x4ae07828,
+	.cm_wkup_wdtimer2_clkctrl		= 0x4ae07830,
+	.cm_wkup_gpio1_clkctrl			= 0x4ae07838,
+	.cm_wkup_gptimer1_clkctrl		= 0x4ae07840,
+	.cm_wkup_gptimer12_clkctrl		= 0x4ae07848,
+	.cm_wkup_sarram_clkctrl			= 0x4ae07860,
+	.cm_wkup_keyboard_clkctrl		= 0x4ae07878,
+	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
+	.prm_vc_val_bypass			= 0x4ae07ba0,
+	.prm_vc_cfg_i2c_mode			= 0x4ae07bb4,
+	.prm_vc_cfg_i2c_clk			= 0x4ae07bb8,
+};
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 5e62013..f2badc1 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -178,7 +178,11 @@  struct watchdog {
 
 /* PRM */
 #define PRM_BASE		0x4AE06000
+#ifndef CONFIG_DRA7XX
 #define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+#else
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1D00)
+#endif
 
 #define PRM_RSTCTRL		PRM_DEVICE_BASE
 #define PRM_RSTCTRL_RESET	0x01
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b632635..a7f63a6 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -53,7 +53,14 @@ 
 #define LPDDR2_IO_REGS_BASE	0x4A100638
 
 /* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+#define CONTROL_CORE_ID_CODE		0x4A002204
+#define CONTROL_WKUP_ID_CODE		0x4AE0C204
+
+#ifndef CONFIG_DRA7XX
+#define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
+#else
+#define CONTROL_ID_CODE		CONTROL_WKUP_ID_CODE
+#endif
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 785daff..97236f7 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -85,6 +85,7 @@  struct prcm_regs {
 	u32 cm_div_h12_dpll_ddrphy;
 	u32 cm_div_h13_dpll_ddrphy;
 	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 cm_clkmode_dpll_dsp;
 	u32 cm_shadow_freq_config1;
 	u32 cm_mpu_mpu_clkctrl;
 
@@ -143,6 +144,11 @@  struct prcm_regs {
 	u32 cm_ssc_deltamstep_dpll_usb;
 	u32 cm_ssc_modfreqdiv_dpll_usb;
 	u32 cm_clkdcoldo_dpll_usb;
+	u32 cm_clkmode_dpll_pcie_ref;
+	u32 cm_clkmode_apll_pcie;
+	u32 cm_idlest_apll_pcie;
+	u32 cm_div_m2_apll_pcie;
+	u32 cm_clkvcoldo_apll_pcie;
 	u32 cm_clkmode_dpll_unipro;
 	u32 cm_idlest_dpll_unipro;
 	u32 cm_autoidle_dpll_unipro;
@@ -160,7 +166,7 @@  struct prcm_regs {
 	u32 cm_l3_2_clkstctrl;
 	u32 cm_l3_2_dynamicdep;
 	u32 cm_l3_2_l3_2_clkctrl;
-	u32 cm_l3_2_gpmc_clkctrl;
+	u32 cm_l3_gpmc_clkctrl;
 	u32 cm_l3_2_ocmc_ram_clkctrl;
 	u32 cm_mpu_m3_clkstctrl;
 	u32 cm_mpu_m3_staticdep;
@@ -205,6 +211,12 @@  struct prcm_regs {
 	u32 cm_cam_clkstctrl;
 	u32 cm_cam_iss_clkctrl;
 	u32 cm_cam_fdif_clkctrl;
+	u32 cm_cam_vip1_clkctrl;
+	u32 cm_cam_vip2_clkctrl;
+	u32 cm_cam_vip3_clkctrl;
+	u32 cm_cam_lvdsrx_clkctrl;
+	u32 cm_cam_csi1_clkctrl;
+	u32 cm_cam_csi2_clkctrl;
 
 	/* cm2.dss */
 	u32 cm_dss_clkstctrl;
@@ -485,6 +497,7 @@  extern struct prcm_regs const **prcm;
 extern struct prcm_regs const omap5_es1_prcm;
 extern struct prcm_regs const omap5_es2_prcm;
 extern struct prcm_regs const omap4_prcm;
+extern struct prcm_regs const dra7xx_prcm;
 extern struct dplls const **dplls_data;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];