diff mbox

[U-Boot,11/14] tegra114: fdt: add SPI blocks

Message ID 1360725802-5518-12-git-send-email-amartin@nvidia.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Allen Martin Feb. 13, 2013, 3:23 a.m. UTC 
Add nodes for t114 SPI controller hardware

Signed-off-by: Allen Martin <amartin@nvidia.com>
---
 arch/arm/dts/tegra114.dtsi |   72 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

Comments

Stephen Warren Feb. 13, 2013, 10:52 p.m. UTC | #1 
On 02/12/2013 08:23 PM, Allen Martin wrote:
> Add nodes for t114 SPI controller hardware

s/t114/Tegra114/. Similar in patch 8/14 subject.

> diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi

> +	spi@7000d400 {
> +		compatible = "nvidia,tegra114-spi";
> +		reg = <0x7000d400 0x200>;
> +		interrupts = <0 59 0x04>;
> +		nvidia,dma-request-selector = <&apbdma 15>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +		/* PERIPH_ID_SBC1, PLLP_OUT0 */
> +		clocks = <&tegra_car 41>;
> +	};

The status property should be last to match the kernel's device tree.
diff mbox

Patch

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f8b4605..a7bd3ca 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -45,4 +45,76 @@ 
 			      0 142 0x04
 			      0 143 0x04>;
 	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
+	};
 };