From patchwork Wed Feb 13 04:31:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Neuling X-Patchwork-Id: 220025 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id EB0D72C02CB for ; Wed, 13 Feb 2013 15:32:55 +1100 (EST) Received: from localhost.localdomain (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 950732C029D; Wed, 13 Feb 2013 15:31:41 +1100 (EST) Received: by localhost.localdomain (Postfix, from userid 1000) id 9B341D44C66; Wed, 13 Feb 2013 15:31:41 +1100 (EST) From: Michael Neuling To: Benjamin Herrenschmidt Subject: [PATCH 01/17] powerpc: Add new CPU feature bit for transactional memory Date: Wed, 13 Feb 2013 15:31:19 +1100 Message-Id: <1360729895-304-2-git-send-email-mikey@neuling.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360729895-304-1-git-send-email-mikey@neuling.org> References: <1360729895-304-1-git-send-email-mikey@neuling.org> Cc: Michael Neuling , linuxppc-dev@lists.ozlabs.org, Matt Evans X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 5f1938f..3636081 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -220,6 +220,13 @@ extern const char *powerpc_base_platform; #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 #endif +/* We only set the TM feature if the kernel was compiled with TM supprt */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +#define CPU_FTR_TM_COMP CPU_FTR_TM +#else +#define CPU_FTR_TM_COMP 0 +#endif + /* We need to mark all pages as being coherent if we're SMP or we have a * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II * require it for PCI "streaming/prefetch" to work properly.