From patchwork Tue Feb 12 18:31:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [2/2] powerpc: Make context bits depend on virtual addr size. Date: Tue, 12 Feb 2013 08:31:45 -0000 From: Aneesh Kumar K.V X-Patchwork-Id: 219936 Message-Id: <1360693905-23503-2-git-send-email-aneesh.kumar@linux.vnet.ibm.com> To: benh@kernel.crashing.org, paulus@samba.org Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" From: "Aneesh Kumar K.V" Different platforms supports different virtual addr size(n bits). We need to mak sure 0:77-n bits of the VA generated is forced to zero. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/mmu-hash64.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index 5f8c2bd..839efae 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -381,7 +381,27 @@ extern void slb_set_size(u16 size); * hash collisions. */ -#define CONTEXT_BITS 19 +/* + * Be careful with this value. This determines the VSID_MODULUS_* and that + * need to be co-prime with VSID_MULTIPLIER* + */ +#if defined(CONFIG_POWER6_CPU) || defined(CONFIG_POWER7_CPU) +/* + * Even if cpu support 68 bits, we limit this to 66 because + * we support only 2^19 context. + */ +#define MAX_VIRTUAL_ADDR_BITS 66 +#else +/* power4,power 5 and cell is 65 */ +#define MAX_VIRTUAL_ADDR_BITS 65 +#endif + +/* + * One bit is taken by the kernel, only the rest of space is available for the + * user space. + */ +#define CONTEXT_BITS (MAX_VIRTUAL_ADDR_BITS - \ + (USER_ESID_BITS + SID_SHIFT + 1)) #define USER_ESID_BITS 18 #define USER_ESID_BITS_1T 6