From patchwork Tue Feb 12 02:00:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 219726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5297A2C02E9 for ; Tue, 12 Feb 2013 13:30:15 +1100 (EST) Received: from localhost ([::1]:52999 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U55Bg-0002aX-FM for incoming@patchwork.ozlabs.org; Mon, 11 Feb 2013 21:01:36 -0500 Received: from eggs.gnu.org ([208.118.235.92]:33755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U55Au-00019O-OX for qemu-devel@nongnu.org; Mon, 11 Feb 2013 21:01:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U55Ag-00060H-FH for qemu-devel@nongnu.org; Mon, 11 Feb 2013 21:00:48 -0500 Received: from ozlabs.org ([203.10.76.45]:49694) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U55Af-0005zW-SM; Mon, 11 Feb 2013 21:00:34 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 5979A2C030E; Tue, 12 Feb 2013 13:00:16 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Tue, 12 Feb 2013 13:00:11 +1100 Message-Id: <1360634411-5518-9-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360634411-5518-1-git-send-email-david@gibson.dropbear.id.au> References: <1360634411-5518-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 203.10.76.45 Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Subject: [Qemu-devel] [PATCH 8/8] target-ppc Disentangle ppc64 hash mmu path for cpu_ppc_handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org cpu_ppc_handle_mmu_fault() calls get_physical_address() (whose behaviour depends on MMU type) then, if that fails, issues an appropriate exception - which again has a number of dependencies on MMU type. This patch starts converting cpu_ppc_handle_mmu_fault() to have a single switch on MMU type, calling MMU specific fault handler functions which deal with both translation and exception delivery appropriately for the MMU type. We convert 64-bit hash MMUs to this new model, but the existing code is left in place for other MMU types for now. Signed-off-by: David Gibson --- target-ppc/cpu.h | 2 ++ target-ppc/mmu-hash64.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++ target-ppc/mmu_helper.c | 37 +++++++------------- 3 files changed, 101 insertions(+), 25 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6143142..da01b06 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1155,6 +1155,8 @@ int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int access_type); +int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, + int mmu_idx); #endif /* defined(TARGET_PPC64) */ #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr (CPUPPCState *env, target_ulong value); diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 0f40e0a..ea5fb1f 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -471,3 +471,90 @@ int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, return get_segment64(env, ctx, eaddr, rw, access_type); } } + +int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, + int mmu_idx) +{ + mmu_ctx_t ctx; + int access_type; + int ret = 0; + + if (rw == 2) { + /* code access */ + rw = 0; + access_type = ACCESS_CODE; + } else { + /* data access */ + access_type = env->access_type; + } + ret = ppc_hash64_get_physical_address(env, &ctx, address, rw, access_type); + if (ret == 0) { + tlb_set_page(env, address & TARGET_PAGE_MASK, + ctx.raddr & TARGET_PAGE_MASK, ctx.prot, + mmu_idx, TARGET_PAGE_SIZE); + ret = 0; + } else if (ret < 0) { + LOG_MMU_STATE(env); + if (access_type == ACCESS_CODE) { + switch (ret) { + case -1: + env->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x40000000; + break; + case -2: + /* Access rights violation */ + env->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x08000000; + break; + case -3: + /* No execute protection violation */ + env->exception_index = POWERPC_EXCP_ISI; + env->error_code = 0x10000000; + break; + case -5: + /* No match in segment table */ + env->exception_index = POWERPC_EXCP_ISEG; + env->error_code = 0; + break; + } + } else { + switch (ret) { + case -1: + /* No matches in page tables or TLB */ + env->exception_index = POWERPC_EXCP_DSI; + env->error_code = 0; + env->spr[SPR_DAR] = address; + if (rw == 1) { + env->spr[SPR_DSISR] = 0x42000000; + } else { + env->spr[SPR_DSISR] = 0x40000000; + } + break; + case -2: + /* Access rights violation */ + env->exception_index = POWERPC_EXCP_DSI; + env->error_code = 0; + env->spr[SPR_DAR] = address; + if (rw == 1) { + env->spr[SPR_DSISR] = 0x0A000000; + } else { + env->spr[SPR_DSISR] = 0x08000000; + } + break; + case -5: + /* No match in segment table */ + env->exception_index = POWERPC_EXCP_DSEG; + env->error_code = 0; + env->spr[SPR_DAR] = address; + break; + } + } +#if 0 + printf("%s: set exception to %d %02x\n", __func__, + env->exception, env->error_code); +#endif + ret = 1; + } + + return ret; +} diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 98143dd..f8f213b 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1533,6 +1533,18 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int access_type; int ret = 0; + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06d: + return ppc_hash64_handle_mmu_fault(env, address, rw, mmu_idx); +#endif + + default: + ; /* Otherwise fall through to the general code below */ + } + if (rw == 2) { /* code access */ rw = 0; @@ -1572,11 +1584,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, break; case POWERPC_MMU_32B: case POWERPC_MMU_601: -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06d: -#endif env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; break; @@ -1621,13 +1628,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, env->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; -#if defined(TARGET_PPC64) - case -5: - /* No match in segment table */ - env->exception_index = POWERPC_EXCP_ISEG; - env->error_code = 0; - break; -#endif } } else { switch (ret) { @@ -1677,11 +1677,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, break; case POWERPC_MMU_32B: case POWERPC_MMU_601: -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06d: -#endif env->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; @@ -1776,14 +1771,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, break; } break; -#if defined(TARGET_PPC64) - case -5: - /* No match in segment table */ - env->exception_index = POWERPC_EXCP_DSEG; - env->error_code = 0; - env->spr[SPR_DAR] = address; - break; -#endif } } #if 0