diff --git a/monitor.c b/monitor.c index 20bd19b..7b2c4da 100644 --- a/monitor.c +++ b/monitor.c @@ -2936,10 +2936,6 @@ static const MonitorDef monitor_defs[] = { { "xer", 0, &monitor_get_xer, }, { "tbu", 0, &monitor_get_tbu, }, { "tbl", 0, &monitor_get_tbl, }, -#if defined(TARGET_PPC64) - /* Address space register */ - { "asr", offsetof(CPUPPCState, asr) }, -#endif /* Segment registers */ { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) }, { "sr0", offsetof(CPUPPCState, sr[0]) }, diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 8c081db..5d04b4c 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -115,8 +115,6 @@ enum powerpc_mmu_t { #define POWERPC_MMU_1TSEG 0x00020000 /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, - /* 620 variant (no segment exceptions) */ - POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003, /* Architecture 2.06 "degraded" (no 1T segments) */ @@ -976,8 +974,6 @@ struct CPUPPCState { /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) - /* Address space register */ - target_ulong asr; /* PowerPC 64 SLB area */ ppc_slb_t slb[64]; int slb_nr; @@ -1501,11 +1497,9 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) #define SPR_PERF3 (0x303) -#define SPR_620_PMC1R (0x303) #define SPR_RCPU_MI_RBA3 (0x303) #define SPR_MPC_MI_EPN (0x303) #define SPR_PERF4 (0x304) -#define SPR_620_PMC2R (0x304) #define SPR_PERF5 (0x305) #define SPR_MPC_MI_TWC (0x305) #define SPR_PERF6 (0x306) @@ -1521,7 +1515,6 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_RCPU_L2U_RBA2 (0x30A) #define SPR_MPC_MD_AP (0x30A) #define SPR_PERFB (0x30B) -#define SPR_620_MMCR0R (0x30B) #define SPR_RCPU_L2U_RBA3 (0x30B) #define SPR_MPC_MD_EPN (0x30B) #define SPR_PERFC (0x30C) @@ -1536,9 +1529,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_UPERF1 (0x311) #define SPR_UPERF2 (0x312) #define SPR_UPERF3 (0x313) -#define SPR_620_PMC1W (0x313) #define SPR_UPERF4 (0x314) -#define SPR_620_PMC2W (0x314) #define SPR_UPERF5 (0x315) #define SPR_UPERF6 (0x316) #define SPR_UPERF7 (0x317) @@ -1546,7 +1537,6 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_UPERF9 (0x319) #define SPR_UPERFA (0x31A) #define SPR_UPERFB (0x31B) -#define SPR_620_MMCR0W (0x31B) #define SPR_UPERFC (0x31C) #define SPR_UPERFD (0x31D) #define SPR_UPERFE (0x31E) @@ -1618,49 +1608,33 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_USDA (0x3AF) #define SPR_40x_ZPR (0x3B0) #define SPR_BOOKE_MAS7 (0x3B0) -#define SPR_620_PMR0 (0x3B0) #define SPR_MMCR2 (0x3B0) #define SPR_PMC5 (0x3B1) #define SPR_40x_PID (0x3B1) -#define SPR_620_PMR1 (0x3B1) #define SPR_PMC6 (0x3B2) #define SPR_440_MMUCR (0x3B2) -#define SPR_620_PMR2 (0x3B2) #define SPR_4xx_CCR0 (0x3B3) #define SPR_BOOKE_EPLC (0x3B3) -#define SPR_620_PMR3 (0x3B3) #define SPR_405_IAC3 (0x3B4) #define SPR_BOOKE_EPSC (0x3B4) -#define SPR_620_PMR4 (0x3B4) #define SPR_405_IAC4 (0x3B5) -#define SPR_620_PMR5 (0x3B5) #define SPR_405_DVC1 (0x3B6) -#define SPR_620_PMR6 (0x3B6) #define SPR_405_DVC2 (0x3B7) -#define SPR_620_PMR7 (0x3B7) #define SPR_BAMR (0x3B7) #define SPR_MMCR0 (0x3B8) -#define SPR_620_PMR8 (0x3B8) #define SPR_PMC1 (0x3B9) #define SPR_40x_SGR (0x3B9) -#define SPR_620_PMR9 (0x3B9) #define SPR_PMC2 (0x3BA) #define SPR_40x_DCWR (0x3BA) -#define SPR_620_PMRA (0x3BA) #define SPR_SIAR (0x3BB) #define SPR_405_SLER (0x3BB) -#define SPR_620_PMRB (0x3BB) #define SPR_MMCR1 (0x3BC) #define SPR_405_SU0R (0x3BC) -#define SPR_620_PMRC (0x3BC) #define SPR_401_SKR (0x3BC) #define SPR_PMC3 (0x3BD) #define SPR_405_DBCR1 (0x3BD) -#define SPR_620_PMRD (0x3BD) #define SPR_PMC4 (0x3BE) -#define SPR_620_PMRE (0x3BE) #define SPR_SDA (0x3BF) -#define SPR_620_PMRF (0x3BF) #define SPR_403_VTBL (0x3CC) #define SPR_403_VTBU (0x3CD) #define SPR_DMISS (0x3D0) @@ -1728,15 +1702,12 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_LDSTCR (0x3F8) #define SPR_L2PMCR (0x3F8) #define SPR_750FX_HID2 (0x3F8) -#define SPR_620_BUSCSR (0x3F8) #define SPR_Exxx_L1FINV0 (0x3F8) #define SPR_L2CR (0x3F9) -#define SPR_620_L2CR (0x3F9) #define SPR_L3CR (0x3FA) #define SPR_750_TDCH (0x3FA) #define SPR_IABR2 (0x3FA) #define SPR_40x_DCCR (0x3FA) -#define SPR_620_L2SR (0x3FA) #define SPR_ICTC (0x3FB) #define SPR_40x_ICCR (0x3FB) #define SPR_THRM1 (0x3FC) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 18e0394..9514891 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -384,7 +384,6 @@ DEF_HELPER_1(load_601_rtcl, tl, env) DEF_HELPER_1(load_601_rtcu, tl, env) #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) -DEF_HELPER_2(store_asr, void, env, tl) DEF_HELPER_1(load_purr, tl, env) #endif DEF_HELPER_2(store_sdr1, void, env, tl) diff --git a/target-ppc/machine.c b/target-ppc/machine.c index e014c0c..168acbe 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -35,7 +35,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32s(f, &fpscr); qemu_put_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) - qemu_put_betls(f, &env->asr); + qemu_put_betls(f, &env->spr[SPR_ASR]); qemu_put_sbe32s(f, &env->slb_nr); #endif qemu_put_betls(f, &env->spr[SPR_SDR1]); @@ -121,7 +121,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->fpscr = fpscr; qemu_get_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) - qemu_get_betls(f, &env->asr); + qemu_get_betls(f, &env->spr[SPR_ASR]); qemu_get_sbe32s(f, &env->slb_nr); #endif qemu_get_betls(f, &sdr1); diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c index 26edcca..616aab6 100644 --- a/target-ppc/misc_helper.c +++ b/target-ppc/misc_helper.c @@ -35,12 +35,6 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) env->spr[sprn]); } #if !defined(CONFIG_USER_ONLY) -#if defined(TARGET_PPC64) -void helper_store_asr(CPUPPCState *env, target_ulong val) -{ - ppc_store_asr(env, val); -} -#endif void helper_store_sdr1(CPUPPCState *env, target_ulong val) { diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 1cc1c16..2f01b31 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1659,7 +1659,6 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, ctx->prot |= PAGE_WRITE; break; #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -1741,7 +1740,6 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, ret = get_bat(env, ctx, eaddr, rw, access_type); } #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -1883,7 +1881,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, case POWERPC_MMU_32B: case POWERPC_MMU_601: #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -1935,14 +1932,8 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, #if defined(TARGET_PPC64) case -5: /* No match in segment table */ - if (env->mmu_model == POWERPC_MMU_620) { - env->exception_index = POWERPC_EXCP_ISI; - /* XXX: this might be incorrect */ - env->error_code = 0x40000000; - } else { - env->exception_index = POWERPC_EXCP_ISEG; - env->error_code = 0; - } + env->exception_index = POWERPC_EXCP_ISEG; + env->error_code = 0; break; #endif } @@ -1995,7 +1986,6 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, case POWERPC_MMU_32B: case POWERPC_MMU_601: #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -2097,21 +2087,9 @@ int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, #if defined(TARGET_PPC64) case -5: /* No match in segment table */ - if (env->mmu_model == POWERPC_MMU_620) { - env->exception_index = POWERPC_EXCP_DSI; - env->error_code = 0; - env->spr[SPR_DAR] = address; - /* XXX: this might be incorrect */ - if (rw == 1) { - env->spr[SPR_DSISR] = 0x42000000; - } else { - env->spr[SPR_DSISR] = 0x40000000; - } - } else { - env->exception_index = POWERPC_EXCP_DSEG; - env->error_code = 0; - env->spr[SPR_DAR] = address; - } + env->exception_index = POWERPC_EXCP_DSEG; + env->error_code = 0; + env->spr[SPR_DAR] = address; break; #endif } @@ -2326,7 +2304,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_32B: case POWERPC_MMU_601: #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -2396,7 +2373,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) tlb_flush_page(env, addr | (0xF << 28)); break; #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: case POWERPC_MMU_2_06: case POWERPC_MMU_2_06d: @@ -2420,16 +2396,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /*****************************************************************************/ /* Special registers manipulation */ -#if defined(TARGET_PPC64) -void ppc_store_asr(CPUPPCState *env, target_ulong value) -{ - if (env->asr != value) { - env->asr = value; - tlb_flush(env, 1); - } -} -#endif - void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2ac5794..a744595 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9524,7 +9524,6 @@ void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) - case POWERPC_MMU_620: case POWERPC_MMU_64B: #endif cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f038850..7dc1b9b 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -372,7 +372,6 @@ static void spr_write_sdr1 (void *opaque, int sprn, int gprn) } /* 64 bits PowerPC specific SPRs */ -/* ASR */ #if defined(TARGET_PPC64) static void spr_read_hior (void *opaque, int gprn, int sprn) { @@ -386,16 +385,6 @@ static void spr_write_hior (void *opaque, int sprn, int gprn) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); tcg_temp_free(t0); } - -static void spr_read_asr (void *opaque, int gprn, int sprn) -{ - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr)); -} - -static void spr_write_asr (void *opaque, int sprn, int gprn) -{ - gen_helper_store_asr(cpu_env, cpu_gpr[gprn]); -} #endif #endif @@ -2142,173 +2131,6 @@ static void gen_spr_compress (CPUPPCState *env) 0x00000000); } -#if defined (TARGET_PPC64) -/* SPR specific to PowerPC 620 */ -static void gen_spr_620 (CPUPPCState *env) -{ - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); - spr_register(env, SPR_ASR, "ASR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_asr, &spr_write_asr, - 0x00000000); - /* Breakpoints */ - /* XXX : not implemented */ - spr_register(env, SPR_IABR, "IABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_DABR, "DABR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_SIAR, "SIAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_SDA, "SDA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMC1R, "PMC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_620_PMC1W, "PMC1", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMC2R, "PMC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_620_PMC2W, "PMC2", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_MMCR0R, "MMCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_620_MMCR0W, "MMCR0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, - 0x00000000); - /* External access control */ - /* XXX : not implemented */ - spr_register(env, SPR_EAR, "EAR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#if 0 // XXX: check this - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR0, "PMR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR1, "PMR1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR2, "PMR2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR3, "PMR3", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR4, "PMR4", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR5, "PMR5", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR6, "PMR6", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR7, "PMR7", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR8, "PMR8", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMR9, "PMR9", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRA, "PMR10", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRB, "PMR11", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRC, "PMR12", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRD, "PMR13", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRE, "PMR14", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_PMRF, "PMR15", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif - /* XXX : not implemented */ - spr_register(env, SPR_620_BUSCSR, "BUSCSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_620_L2SR, "L2SR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} -#endif /* defined (TARGET_PPC64) */ - static void gen_spr_5xx_8xx (CPUPPCState *env) { /* Exception processing */ @@ -2984,31 +2806,6 @@ static void init_excp_604 (CPUPPCState *env) #endif } -#if defined(TARGET_PPC64) -static void init_excp_620 (CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; - env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; - env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; - env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; - env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; - env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; - env->hreset_excp_prefix = 0xFFF00000UL; - /* Hardware reset vector */ - env->hreset_vector = 0x0000000000000100ULL; -#endif -} -#endif /* defined(TARGET_PPC64) */ - static void init_excp_7x0 (CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -6757,47 +6554,6 @@ static void init_proc_POWER7 (CPUPPCState *env) } #endif /* TARGET_PPC64 */ -/* PowerPC 620 */ -#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \ - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ - PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ - PPC_MEM_SYNC | PPC_MEM_EIEIO | \ - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ - PPC_SEGMENT | PPC_EXTERN | \ - PPC_64B | PPC_SLBI) -#define POWERPC_INSNS2_620 (PPC_NONE) -#define POWERPC_MSRM_620 (0x800000000005FF77ULL) -//#define POWERPC_MMU_620 (POWERPC_MMU_620) -#define POWERPC_EXCP_620 (POWERPC_EXCP_970) -#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx) -#define POWERPC_BFDM_620 (bfd_mach_ppc64) -#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ - POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) -#define check_pow_620 check_pow_nocheck /* Check this */ - -__attribute__ (( unused )) -static void init_proc_620 (CPUPPCState *env) -{ - gen_spr_ne_601(env); - gen_spr_620(env); - /* Time base */ - gen_tbl(env); - /* Hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - gen_low_BATs(env); - init_excp_620(env); - env->dcache_line_size = 64; - env->icache_line_size = 64; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env); -} #endif /* defined (TARGET_PPC64) */ /* Default 32 bits PowerPC target will be 604 */ @@ -9244,10 +9000,6 @@ static const ppc_def_t ppc_defs[] = { POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455), /* 64 bits PowerPC */ #if defined (TARGET_PPC64) - /* PowerPC 620 */ - POWERPC_DEF("620", CPU_POWERPC_620, 620), - /* Code name for PowerPC 620 */ - POWERPC_DEF("Trident", CPU_POWERPC_620, 620), #if defined (TODO) /* PowerPC 630 (POWER3) */ POWERPC_DEF("630", CPU_POWERPC_630, 630), @@ -10122,9 +9874,6 @@ static void ppc_cpu_realize(Object *obj, Error **errp) case POWERPC_MMU_64B: mmu_model = "PowerPC 64"; break; - case POWERPC_MMU_620: - mmu_model = "PowerPC 620"; - break; #endif default: mmu_model = "Unknown or invalid";