From patchwork Sun Feb 10 18:30:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 219509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DFB4F2C0292 for ; Mon, 11 Feb 2013 05:31:35 +1100 (EST) Received: from localhost ([::1]:37533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U4bgb-0005BQ-Tu for incoming@patchwork.ozlabs.org; Sun, 10 Feb 2013 13:31:33 -0500 Received: from eggs.gnu.org ([208.118.235.92]:58759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U4bgH-0004oG-9U for qemu-devel@nongnu.org; Sun, 10 Feb 2013 13:31:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U4bgD-0000YN-GD for qemu-devel@nongnu.org; Sun, 10 Feb 2013 13:31:12 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:62477) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U4bgD-0000YD-74 for qemu-devel@nongnu.org; Sun, 10 Feb 2013 13:31:09 -0500 Received: by mail-pa0-f54.google.com with SMTP id fa10so2820318pad.27 for ; Sun, 10 Feb 2013 10:31:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=cGEX+RXTZDg55Fc3/cX6cw9dcMVKnSoh5xS8AMXV6/M=; b=fdySCNl+S+ZujZuh1CnMljdHgYWtRl3iFuQXv/iOtc/SxhimthosYlrjml5CSBfhoT LeIDHRRic7gOjkyt2FIPpjOBwNCnQ0Ndy/ciOSQIGn3RKpWr8VrFhtttxtp9/Ev7x9Ic +RHaAfiSM4kp8n3Gjx2PHYBPOQ+K9gYrETWLhjh0hIu5/xsYl2moNMu1fV+OHgDM2dpS H0wiSouFZZsNKGrRTUj+oFZIVx4JdL7WbvUlj4nol+W0d2NKyKf+5t1jDzN+3TzFNhO5 jKmRTJca6+wYM0z+BUC3701KUxBEhH84EYylI0e8o7Ug/OYt58A7hIkaGkbt9/LA/GGl Ok5A== X-Received: by 10.68.189.197 with SMTP id gk5mr12647662pbc.21.1360521068578; Sun, 10 Feb 2013 10:31:08 -0800 (PST) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id rk5sm5105766pbb.21.2013.02.10.10.31.06 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 10 Feb 2013 10:31:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2013 10:30:46 -0800 Message-Id: <1360521050-29680-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1360521050-29680-1-git-send-email-rth@twiddle.net> References: <1360521050-29680-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.54 Cc: peter.maydell@linaro.org, riku.voipio@iki.fi, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 06/10] mips64-linux-user: Enable 64-bit address mode and fpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-mips/translate.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 3b77b53..b3b8dc6 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15972,6 +15972,14 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); +# ifdef TARGET_MIPS64 + /* Enable 64-bit register mode. */ + env->CP0_Status |= (1 << CP0St_PX); +# endif +# ifdef TARGET_ABI_MIPSN64 + /* Enable 64-bit address mode. */ + env->CP0_Status |= (1 << CP0St_UX); +# endif /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR hardware registers. */ env->CP0_HWREna |= 0x0000000F; @@ -15981,6 +15989,11 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } + /* Enable 64-bit FPU if the target cpu supports it. */ + env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->CP0_Status |= (1 << CP0St_FR); + } #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot,