Patchwork clk: tegra: No 7.1 super clk dividers on Tegra20

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Submitter Peter De Schrijver
Date Feb. 8, 2013, 12:44 p.m.
Message ID <1360327453-29242-1-git-send-email-pdeschrijver@nvidia.com>
Download mbox | patch
Permalink /patch/219129/
State Accepted, archived
Headers show

Comments

Peter De Schrijver - Feb. 8, 2013, 12:44 p.m.
Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
Remove the clocks related to the divider.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-tegra20.c |   36 ++----------------------------------
 1 files changed, 2 insertions(+), 34 deletions(-)
Stephen Warren - Feb. 8, 2013, 5:38 p.m.
On 02/08/2013 05:44 AM, Peter De Schrijver wrote:
> Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
> Remove the clocks related to the divider.

I assume there's no particular need to take this for 3.9; it can wait
until 3.10?
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Peter De Schrijver - Feb. 11, 2013, 9:52 a.m.
On Fri, Feb 08, 2013 at 06:38:39PM +0100, Stephen Warren wrote:
> On 02/08/2013 05:44 AM, Peter De Schrijver wrote:
> > Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
> > Remove the clocks related to the divider.
> 
> I assume there's no particular need to take this for 3.9; it can wait
> until 3.10?

No. There isn't. These clocks aren't used yet because we don't have CPU DVFS.

Cheers,

Peter.
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Stephen Warren - March 6, 2013, 8:40 p.m.
On 02/08/2013 05:44 AM, Peter De Schrijver wrote:
> Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
> Remove the clocks related to the divider.

I have applied this to Tegra's for-3.10/fixes branch.
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Patch

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 4612b2e..90ae8f3 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -711,8 +711,8 @@  static void tegra20_pll_init(void)
 }
 
 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
-				      "pll_p_cclk", "pll_p_out4_cclk",
-				      "pll_p_out3_cclk", "clk_d", "pll_x" };
+				      "pll_p", "pll_p_out4",
+				      "pll_p_out3", "clk_d", "pll_x" };
 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
 				      "pll_p_out3", "pll_p_out2", "clk_d",
 				      "clk_32k", "pll_m_out1" };
@@ -721,38 +721,6 @@  static void tegra20_super_clk_init(void)
 {
 	struct clk *clk;
 
-	/*
-	 * DIV_U71 dividers for CCLK, these dividers are used only
-	 * if parent clock is fixed rate.
-	 */
-
-	/*
-	 * Clock input to cclk divided from pll_p using
-	 * U71 divider of cclk.
-	 */
-	clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
-				clk_base + SUPER_CCLK_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
-	/*
-	 * Clock input to cclk divided from pll_p_out3 using
-	 * U71 divider of cclk.
-	 */
-	clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
-				clk_base + SUPER_CCLK_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
-	/*
-	 * Clock input to cclk divided from pll_p_out4 using
-	 * U71 divider of cclk.
-	 */
-	clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
-				clk_base + SUPER_CCLK_DIVIDER, 0,
-				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
-	clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
 	/* CCLK */
 	clk = tegra_clk_register_super_mux("cclk", cclk_parents,
 			      ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,