diff mbox

target-i386: n270 can MOVBE

Message ID 20130208121743.GD14526@pd.tnic
State New
Headers show

Commit Message

Borislav Petkov Feb. 8, 2013, 12:17 p.m. UTC 
Hi Andreas,

On Fri, Feb 08, 2013 at 12:38:03PM +0100, Andreas Färber wrote:
> Am 08.02.2013 10:30, schrieb Borislav Petkov:
> > From: Borislav Petkov <bp@suse.de>
> > 
> > The Atom core (cpu name "n270" in QEMU speak) supports MOVBE. This is
> > needed when booting 3.8 and later linux kernels built with the MATOM
> > target because we require MOVBE in order to boot properly now.
> > 
> > Cc: "H. Peter Anvin" <hpa@zytor.com>
> > Cc: Richard Henderson <rth@twiddle.net>
> > Signed-off-by: Borislav Petkov <bp@suse.de>
> 
> Please CC me on cpu.c changes (cf. MAINTAINERS).

Wow, qemu has get_maintainer.pl too:

$ git show HEAD | ./scripts/get_maintainer.pl
"Andreas Färber" <afaerber@suse.de> (supporter:CPU)
qemu-devel@nongnu.org (odd fixer:X86

:-)

Ok, fixed.

> >          .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
> > -            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
> > +            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
> > +	    CPUID_EXT_MOVBE,
> 
> Tab. Please use scripts/checkpatch.pl to verify before sending.

Done.

> >          .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
> >              CPUID_EXT2_NX,
> >          .ext3_features = CPUID_EXT3_LAHF_LM,
> 
> Otherwise if someone can ack (or if you can point me to a manual), this
> looks like a good bugfix for v1.4.

Right, I don't know what v1.4 is but this still needs Richard's patchset
enabling MOVBE dynamic translation in qemu to go in first before
enabling MOVBE for the n270 model.

Anyway, fixed patch is below.

> CC'ing some more CPU'ish people.

Well, if you do cat /proc/cpuinfo on an Atom, you can see movbe there.

Here it is from my atom box:

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 28
model name      : Intel(R) Atom(TM) CPU N270   @ 1.60GHz
stepping        : 2
microcode       : 0x208
cpu MHz         : 800.000
cache size      : 512 KB
physical id     : 0
siblings        : 1
core id         : 0
cpu cores       : 1
apicid          : 0
initial apicid  : 0
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 10
wp              : yes
flags           : fpu vme de tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 xtpr pdcm movbe lahf_lm dtherm
bogomips        : 3192.01
clflush size    : 64
cache_alignment : 64
address sizes   : 32 bits physical, 32 bits virtual
power management:

Or, more cpu vendor-y, do CPUID.EAX(1) on an n270 and bit 22 in ECX is
set. Here is a full base cpuid leafs dump:

$ ./dump_cpuid
max base function: 0x0000000a
CPUID.EAX=0x00000000
EAX=0x0000000a, EBX=0x756e6547, ECX=0x6c65746e, EDX=0x49656e69
CPUID.EAX=0x00000001
EAX=0x000106c2, EBX=0x01020800, ECX=0x0040c39d, EDX=0xbfe9fbff
				    ^^^^^
				    bit 22 here is MOVBE presence.

CPUID.EAX=0x00000002
EAX=0x4fba5901, EBX=0x0e3080c0, ECX=0x00000000, EDX=0x00000000
CPUID.EAX=0x00000003
EAX=0x00000000, EBX=0x00000000, ECX=0x00000000, EDX=0x00000000
CPUID.EAX=0x00000004
EAX=0x00004121, EBX=0x0140003f, ECX=0x0000003f, EDX=0x00000001
CPUID.EAX=0x00000005
EAX=0x00000040, EBX=0x00000040, ECX=0x00000003, EDX=0x00020220
CPUID.EAX=0x00000006
EAX=0x00000001, EBX=0x00000002, ECX=0x00000001, EDX=0x00000000
CPUID.EAX=0x00000007
EAX=0x00000000, EBX=0x00000000, ECX=0x00000000, EDX=0x00000000
CPUID.EAX=0x00000008
EAX=0x00000000, EBX=0x00000000, ECX=0x00000000, EDX=0x00000000
CPUID.EAX=0x00000009
EAX=0x00000000, EBX=0x00000000, ECX=0x00000000, EDX=0x00000000
CPUID.EAX=0x0000000a
EAX=0x07280203, EBX=0x00000000, ECX=0x00000000, EDX=0x00002501

And the official document is this one here:

http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html

Table 5-5 Feature Flags Reported in the ECX Register (Sheet 1 of 2).

HTH.

--
From 5371732b65fbb9a873b52c67a260ffcaf7caf88d Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Fri, 8 Feb 2013 10:19:44 +0100
Subject: [PATCH] target-i386: n270 can MOVBE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Atom core (cpu name "n270" in QEMU speak) supports MOVBE. This is
needed when booting 3.8 and later linux kernels built with the MATOM
target because we require MOVBE in order to boot properly now.

Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Andreas Färber" <afaerber@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 target-i386/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Andreas Färber Feb. 8, 2013, 1:44 p.m. UTC | #1 
Hi,

Am 08.02.2013 13:17, schrieb Borislav Petkov:
> On Fri, Feb 08, 2013 at 12:38:03PM +0100, Andreas Färber wrote:
>> Am 08.02.2013 10:30, schrieb Borislav Petkov:
>>>          .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
>>>              CPUID_EXT2_NX,
>>>          .ext3_features = CPUID_EXT3_LAHF_LM,
>>
>> Otherwise if someone can ack (or if you can point me to a manual), this
>> looks like a good bugfix for v1.4.
> 
> Right, I don't know what v1.4 is

It's the QEMU release that we're about to make in a week. :-)
http://wiki.qemu.org/Planning/1.4

> but this still needs Richard's patchset
> enabling MOVBE dynamic translation in qemu to go in first before
> enabling MOVBE for the n270 model.

OK, so this goes through Richard's queue then, no objections.

Cheers,
Andreas
Paolo Bonzini Feb. 8, 2013, 1:59 p.m. UTC | #2 
Il 08/02/2013 14:44, Andreas Färber ha scritto:
>>> >> Otherwise if someone can ack (or if you can point me to a manual), this
>>> >> looks like a good bugfix for v1.4.
>> > 
>> > Right, I don't know what v1.4 is
> It's the QEMU release that we're about to make in a week. :-)
> http://wiki.qemu.org/Planning/1.4
> 
>> > but this still needs Richard's patchset
>> > enabling MOVBE dynamic translation in qemu to go in first before
>> > enabling MOVBE for the n270 model.
> OK, so this goes through Richard's queue then, no objections.

I'm not sure I understand the relationship between QEMU CPUID bits and
TCG/KVM, but perhaps this could go in 1.4 for KVM.

Does TCG have a way to mask bits that aren't supported in the
translator?  For example AVX that is enabled by SandyBridge.

Paolo
Eduardo Habkost Feb. 8, 2013, 3:10 p.m. UTC | #3 
On Fri, Feb 08, 2013 at 02:59:25PM +0100, Paolo Bonzini wrote:
> Il 08/02/2013 14:44, Andreas Färber ha scritto:
> >>> >> Otherwise if someone can ack (or if you can point me to a manual), this
> >>> >> looks like a good bugfix for v1.4.
> >> > 
> >> > Right, I don't know what v1.4 is
> > It's the QEMU release that we're about to make in a week. :-)
> > http://wiki.qemu.org/Planning/1.4
> > 
> >> > but this still needs Richard's patchset
> >> > enabling MOVBE dynamic translation in qemu to go in first before
> >> > enabling MOVBE for the n270 model.
> > OK, so this goes through Richard's queue then, no objections.
> 
> I'm not sure I understand the relationship between QEMU CPUID bits and
> TCG/KVM, but perhaps this could go in 1.4 for KVM.
> 
> Does TCG have a way to mask bits that aren't supported in the
> translator?  For example AVX that is enabled by SandyBridge.

TCG mode automatically masks the bits not supported by TCG, see how
x86_cpu_realizefn() uses TCG_FEATURES/TCG_EXT_FEATURES/etc.
Paolo Bonzini Feb. 8, 2013, 3:19 p.m. UTC | #4 
Il 08/02/2013 16:10, Eduardo Habkost ha scritto:
> On Fri, Feb 08, 2013 at 02:59:25PM +0100, Paolo Bonzini wrote:
>> Il 08/02/2013 14:44, Andreas Färber ha scritto:
>>>>>>> Otherwise if someone can ack (or if you can point me to a manual), this
>>>>>>> looks like a good bugfix for v1.4.
>>>>>
>>>>> Right, I don't know what v1.4 is
>>> It's the QEMU release that we're about to make in a week. :-)
>>> http://wiki.qemu.org/Planning/1.4
>>>
>>>>> but this still needs Richard's patchset
>>>>> enabling MOVBE dynamic translation in qemu to go in first before
>>>>> enabling MOVBE for the n270 model.
>>> OK, so this goes through Richard's queue then, no objections.
>>
>> I'm not sure I understand the relationship between QEMU CPUID bits and
>> TCG/KVM, but perhaps this could go in 1.4 for KVM.
>>
>> Does TCG have a way to mask bits that aren't supported in the
>> translator?  For example AVX that is enabled by SandyBridge.
> 
> TCG mode automatically masks the bits not supported by TCG, see how
> x86_cpu_realizefn() uses TCG_FEATURES/TCG_EXT_FEATURES/etc.

Uh, but n270 doesn't support vmx. :(  Too bad.  Then this patch indeed
is not needed in 1.4.

Paolo
diff mbox

Patch

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4a516e1f9e25..36a133462a8d 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -620,7 +620,8 @@  static x86_def_t builtin_x86_defs[] = {
             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
             /* Some CPUs got no CPUID_SEP */
         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
-            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
+            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
+            CPUID_EXT_MOVBE,
         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
             CPUID_EXT2_NX,
         .ext3_features = CPUID_EXT3_LAHF_LM,