From patchwork Fri Feb 8 10:04:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 219097 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 936FD2C008C for ; Fri, 8 Feb 2013 21:11:00 +1100 (EST) Received: from localhost ([::1]:47871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3kv4-0001M6-Km for incoming@patchwork.ozlabs.org; Fri, 08 Feb 2013 05:10:58 -0500 Received: from eggs.gnu.org ([208.118.235.92]:59670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3kum-00016m-H7 for qemu-devel@nongnu.org; Fri, 08 Feb 2013 05:10:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U3kui-0003Yy-14 for qemu-devel@nongnu.org; Fri, 08 Feb 2013 05:10:40 -0500 Received: from tx2ehsobe002.messaging.microsoft.com ([65.55.88.12]:50426 helo=tx2outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3kuV-0003WV-AV; Fri, 08 Feb 2013 05:10:23 -0500 Received: from mail186-tx2-R.bigfish.com (10.9.14.247) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 14.1.225.23; Fri, 8 Feb 2013 10:10:22 +0000 Received: from mail186-tx2 (localhost [127.0.0.1]) by mail186-tx2-R.bigfish.com (Postfix) with ESMTP id 654FC4015D; Fri, 8 Feb 2013 10:10:22 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 6 X-BigFish: VS6(zz853kzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ah1082kzz8275bhz2dh2a8h668h839hd24he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1155h) Received: from mail186-tx2 (localhost.localdomain [127.0.0.1]) by mail186-tx2 (MessageSwitch) id 1360318220295648_21996; Fri, 8 Feb 2013 10:10:20 +0000 (UTC) Received: from TX2EHSMHS018.bigfish.com (unknown [10.9.14.251]) by mail186-tx2.bigfish.com (Postfix) with ESMTP id 3A3FB2009C; Fri, 8 Feb 2013 10:10:20 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS018.bigfish.com (10.9.99.118) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 8 Feb 2013 10:10:19 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Fri, 8 Feb 2013 10:10:19 +0000 Received: from freescale.com ([10.232.15.72]) by az84smr01.freescale.net (8.14.3/8.14.0) with SMTP id r18AAF7T008389; Fri, 8 Feb 2013 03:10:16 -0700 Received: by freescale.com (sSMTP sendmail emulation); Fri, 08 Feb 2013 15:35:07 +0530 From: Bharat Bhushan To: , , , Date: Fri, 8 Feb 2013 15:34:56 +0530 Message-ID: <1360317896-22666-2-git-send-email-bharat.bhushan@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1360317896-22666-1-git-send-email-bharat.bhushan@freescale.com> References: <1360317896-22666-1-git-send-email-bharat.bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 65.55.88.12 Cc: Bharat Bhushan Subject: [Qemu-devel] [PATCH v4] Enable kvm emulated watchdog X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Enable the KVM emulated watchdog if KVM supports (use the capability enablement in watchdog handler). Also watchdog exit (KVM_EXIT_WATCHDOG) handling is added. Watchdog state machine is cleared whenever VM state changes to running. This is to handle the cases like return from debug halt etc. Signed-off-by: Bharat Bhushan --- hw/ppc_booke.c | 43 +++++++++++++++++++++- target-ppc/kvm.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++ target-ppc/kvm_ppc.h | 33 +++++++++++++++++ 3 files changed, 173 insertions(+), 2 deletions(-) diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c index 25a4e91..1eb8415 100644 --- a/hw/ppc_booke.c +++ b/hw/ppc_booke.c @@ -28,7 +28,7 @@ #include "nvram.h" #include "qemu/log.h" #include "loader.h" - +#include "kvm_ppc.h" /* Timer Control Register */ @@ -211,6 +211,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val) PowerPCCPU *cpu = ppc_env_get_cpu(env); env->spr[SPR_BOOKE_TSR] &= ~val; + kvmppc_clear_tsr_bits(cpu, val); booke_update_irq(cpu); } @@ -222,6 +223,7 @@ void store_booke_tcr(CPUPPCState *env, target_ulong val) tb_env = env->tb_env; env->spr[SPR_BOOKE_TCR] = val; + kvmppc_set_tcr(cpu); booke_update_irq(cpu); @@ -234,7 +236,6 @@ void store_booke_tcr(CPUPPCState *env, target_ulong val) booke_get_wdt_target(env, tb_env), &booke_timer->wdt_next, booke_timer->wdt_timer); - } static void ppc_booke_timer_reset_handle(void *opaque) @@ -244,14 +245,40 @@ static void ppc_booke_timer_reset_handle(void *opaque) env->spr[SPR_BOOKE_TSR] = 0; env->spr[SPR_BOOKE_TCR] = 0; + kvmppc_sync_set_timer_regs(cpu); booke_update_irq(cpu); } +/* + * This function will be called whenever the CPU state changes. + * CPU states are defined "typedef enum RunState". + * Regarding timer, When CPU state changes to running after debug halt + * or similar cases which takes time then in between final watchdog + * expiry happenes. This will cause exit to QEMU and configured watchdog + * action will be taken. To avoid this we always clear the watchdog state when + * state changes to running. + */ +static void cpu_state_change_handler(void *opaque, int running, RunState state) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + + if (!running) { + return; + } + + /* + * Clear watchdog interrupt condition by clearing TSR. + */ + store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK); +} + void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) { ppc_tb_t *tb_env; booke_timer_t *booke_timer; + int ret = 0; tb_env = g_malloc0(sizeof(ppc_tb_t)); booke_timer = g_malloc0(sizeof(booke_timer_t)); @@ -269,5 +296,17 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) booke_timer->wdt_timer = qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu); + ret = kvmppc_booke_watchdog_enable(cpu); + + if (ret) { + /* TODO: Start the QEMU emulated watchdog if not running on KVM. + * Also start the QEMU emulated watchdog if KVM does not support + * emulated watchdog or somehow it is not enabled (supported but + * not enabled is though some bug and requires debugging :)). + */ + } + + qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu); + qemu_register_reset(ppc_booke_timer_reset_handle, cpu); } diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 2c64c63..d0898f5 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -36,6 +36,7 @@ #include "hw/sysbus.h" #include "hw/spapr.h" #include "hw/spapr_vio.h" +#include "hw/watchdog.h" //#define DEBUG_KVM @@ -61,6 +62,7 @@ static int cap_ppc_smt; static int cap_ppc_rma; static int cap_spapr_tce; static int cap_hior; +static int cap_ppc_watchdog; /* XXX We have a race condition where we actually have a level triggered * interrupt, but the infrastructure can't expose that yet, so the guest @@ -90,6 +92,7 @@ int kvm_arch_init(KVMState *s) cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA); cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); + cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); if (!cap_interrupt_level) { fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " @@ -856,6 +859,12 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) run->epr.epr = ldl_phys(env->mpic_iack); ret = 0; break; + case KVM_EXIT_WATCHDOG: + dprintf("handle watchdog expiry\n"); + watchdog_perform_action(); + ret = 0; + break; + default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); ret = -1; @@ -865,6 +874,96 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) return ret; } +void kvmppc_sync_get_timer_regs(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + if (kvm_enabled()) { + cpu_synchronize_state(env); + } +} + +int kvmppc_sync_set_timer_regs(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + CPUState *cs = CPU(cpu); + struct kvm_sregs sregs; + + if (!kvm_enabled() || !cap_booke_sregs) { + return -1; + } + + sregs.u.e.tsr = env->spr[SPR_BOOKE_TSR]; + sregs.u.e.tcr = env->spr[SPR_BOOKE_TCR]; + sregs.u.e.update_special = KVM_SREGS_E_BASE | KVM_SREGS_E_UPDATE_TSR; + + return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); +} + +int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) +{ + CPUState *cs = CPU(cpu); + uint32_t bits = tsr_bits; + struct kvm_one_reg reg = { + .id = KVM_REG_PPC_OR_TSR, + .addr = (uintptr_t) &bits, + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); +} + +int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) +{ + + CPUState *cs = CPU(cpu); + uint32_t bits = tsr_bits; + struct kvm_one_reg reg = { + .id = KVM_REG_PPC_CLEAR_TSR, + .addr = (uintptr_t) &bits, + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); +} + +int kvmppc_set_tcr(PowerPCCPU *cpu) +{ + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; + uint32_t tcr = env->spr[SPR_BOOKE_TCR]; + + struct kvm_one_reg reg = { + .id = KVM_REG_PPC_SET_TCR, + .addr = (uintptr_t) &tcr, + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); +} + +int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) +{ + CPUState *cs = CPU(cpu); + struct kvm_enable_cap encap = {}; + int ret; + + if (!kvm_enabled()) { + return -1; + } + + if (!cap_ppc_watchdog) { + printf("warning: KVM does not support watchdog"); + return -1; + } + + encap.cap = KVM_CAP_PPC_BOOKE_WATCHDOG; + ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); + if (ret < 0) { + fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", + __func__, strerror(-ret)); + return ret; + } + + return ret; +} + static int read_cpuinfo(const char *field, char *value, int len) { FILE *f; diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h index c30b006..f0bf95a 100644 --- a/target-ppc/kvm_ppc.h +++ b/target-ppc/kvm_ppc.h @@ -27,6 +27,12 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level); void kvmppc_set_papr(PowerPCCPU *cpu); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); int kvmppc_smt_threads(void); +void kvmppc_sync_get_timer_regs(PowerPCCPU *cpu); +int kvmppc_sync_set_timer_regs(PowerPCCPU *cpu); +int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits); +int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits); +int kvmppc_set_tcr(PowerPCCPU *cpu); +int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu); #ifndef CONFIG_USER_ONLY off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem); void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd); @@ -90,6 +96,33 @@ static inline int kvmppc_smt_threads(void) { return 1; } +static void kvmppc_sync_get_timer_regs(PowerPCCPU *cpu) +{ +} + +static int kvmppc_sync_set_timer_regs(PowerPCCPU *cpu) +{ + return 0; +} + +int kvmppc_or_tsr_bits(PowerPCCPU *cpu, u32 tsr_bits) +{ + return 0; +} +int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, u32 tsr_bits) +{ + return 0; +} + +int kvmppc_set_tcr(PowerPCCPU *cpu) +{ + return 0; +} + +static inline int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) +{ + return -1; +} #ifndef CONFIG_USER_ONLY static inline off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem)