From patchwork Fri Feb 8 04:03:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 219038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AEB372C0077 for ; Fri, 8 Feb 2013 15:04:26 +1100 (EST) Received: from localhost ([::1]:46937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3fCH-0001nz-8U for incoming@patchwork.ozlabs.org; Thu, 07 Feb 2013 23:04:21 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3fBx-0001af-I8 for qemu-devel@nongnu.org; Thu, 07 Feb 2013 23:04:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U3fBv-0003rQ-U3 for qemu-devel@nongnu.org; Thu, 07 Feb 2013 23:04:01 -0500 Received: from va3ehsobe001.messaging.microsoft.com ([216.32.180.11]:55697 helo=va3outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U3fBv-0003rI-Os for qemu-devel@nongnu.org; Thu, 07 Feb 2013 23:03:59 -0500 Received: from mail210-va3-R.bigfish.com (10.7.14.238) by VA3EHSOBE014.bigfish.com (10.7.40.64) with Microsoft SMTP Server id 14.1.225.23; Fri, 8 Feb 2013 04:03:59 +0000 Received: from mail210-va3 (localhost [127.0.0.1]) by mail210-va3-R.bigfish.com (Postfix) with ESMTP id 1B98A58018D; Fri, 8 Feb 2013 04:03:59 +0000 (UTC) X-Forefront-Antispam-Report: CIP:149.199.60.83; KIP:(null); UIP:(null); IPV:NLI; H:xsj-gw1; RD:unknown-60-83.xilinx.com; EFVD:NLI X-SpamScore: 1 X-BigFish: VPS1(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2fh95h668h839hd24hf0ah119dh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h906i1155h) Received-SPF: pass (mail210-va3: domain of xilinx.com designates 149.199.60.83 as permitted sender) client-ip=149.199.60.83; envelope-from=peter.crosthwaite@xilinx.com; helo=xsj-gw1 ; helo=xsj-gw1 ; Received: from mail210-va3 (localhost.localdomain [127.0.0.1]) by mail210-va3 (MessageSwitch) id 1360296237557092_21493; Fri, 8 Feb 2013 04:03:57 +0000 (UTC) Received: from VA3EHSMHS008.bigfish.com (unknown [10.7.14.242]) by mail210-va3.bigfish.com (Postfix) with ESMTP id 84F7FB40053; Fri, 8 Feb 2013 04:03:57 +0000 (UTC) Received: from xsj-gw1 (149.199.60.83) by VA3EHSMHS008.bigfish.com (10.7.99.18) with Microsoft SMTP Server id 14.1.225.23; Fri, 8 Feb 2013 04:03:53 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1.xilinx.com) by xsj-gw1 with esmtp (Exim 4.63) (envelope-from ) id 1U3fBp-00052g-05; Thu, 07 Feb 2013 20:03:53 -0800 From: Peter Crosthwaite To: Date: Fri, 8 Feb 2013 14:03:48 +1000 X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: X-RCIS-Action: ALLOW MIME-Version: 1.0 Message-ID: X-OriginatorOrg: xilinx.com X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 216.32.180.11 Cc: edgar.iglesias@gmail.com, aliguori@us.ibm.com, Peter Crosthwaite Subject: [Qemu-devel] [PATCH v1 1/6] arm: mptimer: CamelCased type names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Trivial find replace on type names "timerblock" and "arm_mptimer_state" to conform with QEMU coding style. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell --- hw/arm_mptimer.c | 56 +++++++++++++++++++++++++++--------------------------- 1 files changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c index 32817d3..de0ef36 100644 --- a/hw/arm_mptimer.c +++ b/hw/arm_mptimer.c @@ -38,16 +38,16 @@ typedef struct { QEMUTimer *timer; qemu_irq irq; MemoryRegion iomem; -} timerblock; +} TimerBlock; typedef struct { SysBusDevice busdev; uint32_t num_cpu; - timerblock timerblock[MAX_CPUS * 2]; + TimerBlock timerblock[MAX_CPUS * 2]; MemoryRegion iomem[2]; -} arm_mptimer_state; +} ARMMPTimerState; -static inline int get_current_cpu(arm_mptimer_state *s) +static inline int get_current_cpu(ARMMPTimerState *s) { CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); @@ -58,18 +58,18 @@ static inline int get_current_cpu(arm_mptimer_state *s) return cpu_single_cpu->cpu_index; } -static inline void timerblock_update_irq(timerblock *tb) +static inline void timerblock_update_irq(TimerBlock *tb) { qemu_set_irq(tb->irq, tb->status); } /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ -static inline uint32_t timerblock_scale(timerblock *tb) +static inline uint32_t timerblock_scale(TimerBlock *tb) { return (((tb->control >> 8) & 0xff) + 1) * 10; } -static void timerblock_reload(timerblock *tb, int restart) +static void timerblock_reload(TimerBlock *tb, int restart) { if (tb->count == 0) { return; @@ -83,7 +83,7 @@ static void timerblock_reload(timerblock *tb, int restart) static void timerblock_tick(void *opaque) { - timerblock *tb = (timerblock *)opaque; + TimerBlock *tb = (TimerBlock *)opaque; tb->status = 1; if (tb->control & 2) { tb->count = tb->load; @@ -97,7 +97,7 @@ static void timerblock_tick(void *opaque) static uint64_t timerblock_read(void *opaque, hwaddr addr, unsigned size) { - timerblock *tb = (timerblock *)opaque; + TimerBlock *tb = (TimerBlock *)opaque; int64_t val; switch (addr) { case 0: /* Load */ @@ -125,7 +125,7 @@ static uint64_t timerblock_read(void *opaque, hwaddr addr, static void timerblock_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - timerblock *tb = (timerblock *)opaque; + TimerBlock *tb = (TimerBlock *)opaque; int64_t old; switch (addr) { case 0: /* Load */ @@ -164,7 +164,7 @@ static void timerblock_write(void *opaque, hwaddr addr, static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, unsigned size) { - arm_mptimer_state *s = (arm_mptimer_state *)opaque; + ARMMPTimerState *s = (ARMMPTimerState *)opaque; int id = get_current_cpu(s); return timerblock_read(&s->timerblock[id * 2], addr, size); } @@ -172,7 +172,7 @@ static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, static void arm_thistimer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - arm_mptimer_state *s = (arm_mptimer_state *)opaque; + ARMMPTimerState *s = (ARMMPTimerState *)opaque; int id = get_current_cpu(s); timerblock_write(&s->timerblock[id * 2], addr, value, size); } @@ -180,7 +180,7 @@ static void arm_thistimer_write(void *opaque, hwaddr addr, static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr, unsigned size) { - arm_mptimer_state *s = (arm_mptimer_state *)opaque; + ARMMPTimerState *s = (ARMMPTimerState *)opaque; int id = get_current_cpu(s); return timerblock_read(&s->timerblock[id * 2 + 1], addr, size); } @@ -188,7 +188,7 @@ static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr, static void arm_thiswdog_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - arm_mptimer_state *s = (arm_mptimer_state *)opaque; + ARMMPTimerState *s = (ARMMPTimerState *)opaque; int id = get_current_cpu(s); timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size); } @@ -223,7 +223,7 @@ static const MemoryRegionOps timerblock_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void timerblock_reset(timerblock *tb) +static void timerblock_reset(TimerBlock *tb) { tb->count = 0; tb->load = 0; @@ -237,8 +237,8 @@ static void timerblock_reset(timerblock *tb) static void arm_mptimer_reset(DeviceState *dev) { - arm_mptimer_state *s = - FROM_SYSBUS(arm_mptimer_state, SYS_BUS_DEVICE(dev)); + ARMMPTimerState *s = + FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev)); int i; /* We reset every timer in the array, not just the ones we're using, * because vmsave will look at every array element. @@ -250,7 +250,7 @@ static void arm_mptimer_reset(DeviceState *dev) static int arm_mptimer_init(SysBusDevice *dev) { - arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev); + ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev); int i; if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) { hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS); @@ -278,7 +278,7 @@ static int arm_mptimer_init(SysBusDevice *dev) "arm_mptimer_wdog", 0x20); sysbus_init_mmio(dev, &s->iomem[1]); for (i = 0; i < (s->num_cpu * 2); i++) { - timerblock *tb = &s->timerblock[i]; + TimerBlock *tb = &s->timerblock[i]; tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb); sysbus_init_irq(dev, &tb->irq); memory_region_init_io(&tb->iomem, &timerblock_ops, tb, @@ -294,11 +294,11 @@ static const VMStateDescription vmstate_timerblock = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(count, timerblock), - VMSTATE_UINT32(load, timerblock), - VMSTATE_UINT32(control, timerblock), - VMSTATE_UINT32(status, timerblock), - VMSTATE_INT64(tick, timerblock), + VMSTATE_UINT32(count, TimerBlock), + VMSTATE_UINT32(load, TimerBlock), + VMSTATE_UINT32(control, TimerBlock), + VMSTATE_UINT32(status, TimerBlock), + VMSTATE_INT64(tick, TimerBlock), VMSTATE_END_OF_LIST() } }; @@ -308,14 +308,14 @@ static const VMStateDescription vmstate_arm_mptimer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2), - 1, vmstate_timerblock, timerblock), + VMSTATE_STRUCT_ARRAY(timerblock, ARMMPTimerState, (MAX_CPUS * 2), + 1, vmstate_timerblock, TimerBlock), VMSTATE_END_OF_LIST() } }; static Property arm_mptimer_properties[] = { - DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0), + DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), DEFINE_PROP_END_OF_LIST() }; @@ -334,7 +334,7 @@ static void arm_mptimer_class_init(ObjectClass *klass, void *data) static const TypeInfo arm_mptimer_info = { .name = "arm_mptimer", .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(arm_mptimer_state), + .instance_size = sizeof(ARMMPTimerState), .class_init = arm_mptimer_class_init, };