Patchwork [U-Boot,v2] mx6: Disable Power Down Bit of watchdog

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Submitter Fabio Estevam
Date Feb. 7, 2013, 4:22 p.m.
Message ID <1360254178-25394-1-git-send-email-fabio.estevam@freescale.com>
Download mbox | patch
Permalink /patch/218949/
State Changes Requested
Headers show

Comments

Fabio Estevam - Feb. 7, 2013, 4:22 p.m.
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able
to reach the Linux prompt.

Comparing the watchdog behaviour on a revB versus revC board:

- On a mx6qsabresd revB:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...

- On a mx6qsabresd revC:

U-Boot > reset
resetting ...

U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR

So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.

Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Improve commit log

 arch/arm/cpu/armv7/mx6/soc.c             |   17 ++++++++++++++++-
 arch/arm/include/asm/arch-mx6/imx-regs.h |    8 ++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

Patch

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a8aad5d..0e4ab36 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -121,12 +121,27 @@  void set_vddsoc(u32 mv)
 	writel(reg, &anatop->reg_core);
 }
 
+static void imx_set_wdog_powerdown(int enable)
+{
+	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+
+	/* Set or Clear PDE - Power Down Enable bit */
+	if (!enable) {
+		writew(0x0, &wdog1->wmcr);
+		writew(0x0, &wdog2->wmcr);
+	} else {
+		writew(0x1, &wdog1->wmcr);
+		writew(0x1, &wdog2->wmcr);
+	}
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
-
+	imx_set_wdog_powerdown(0); /* Disable PDE bit of WMCR register */
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3eb0081..eaa7439 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -601,5 +601,13 @@  struct iomuxc_base_regs {
 	u32     daisy[104];     /* 0x7b0..94c */
 };
 
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */