Patchwork [RFC] powerpc: add Book E support to 64-bit hibernation

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Submitter Dongsheng Wang
Date Feb. 7, 2013, 2:25 a.m.
Message ID <1360203915-22112-1-git-send-email-dongsheng.wang@freescale.com>
Download mbox | patch
Permalink /patch/218817/
State Superseded
Headers show

Comments

Dongsheng Wang - Feb. 7, 2013, 2:25 a.m.
Update the 64-bit hibernation code to support Book E CPUs.
Some registers and instructions are not defined for Book3e
(SDR reg, tlbia instruction).
SDR: Storage Description Register. Book3S and Book3E have different
address translation mode, we do not need HTABORG & HTABSIZE to
translate virtual address to real address.
More registers are saved in BookE-64bit.(TCR, SPRGx)

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---

Hopefully someone can give me some advice about cache flush. It
confused me that why only 1 MiB is flushed from KERNEL_START on
Book3S. Is there a need to flush L2 cache if I have already flushed
L1 cache? If yes, how about L3 cache? Cache levels are different
in cores, the instruction sets may also be different.

 1 files changed, 62 insertions(+), 2 deletions(-)
Wang Dongsheng-B40534 - Feb. 22, 2013, 7:35 a.m.
Hi Benjamin & Johannes,

Any thoughts about this patch?

> -----Original Message-----
> From: Wang Dongsheng-B40534
> Sent: Thursday, February 07, 2013 10:25 AM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: Wood Scott-B07421; Li Yang-R58472; Zhao Chenhui-B35336; Wang
> Dongsheng-B40534
> Subject: [RFC][PATCH] powerpc: add Book E support to 64-bit hibernation
> 
> Update the 64-bit hibernation code to support Book E CPUs.
> Some registers and instructions are not defined for Book3e
> (SDR reg, tlbia instruction).
> SDR: Storage Description Register. Book3S and Book3E have different
> address translation mode, we do not need HTABORG & HTABSIZE to
> translate virtual address to real address.
> More registers are saved in BookE-64bit.(TCR, SPRGx)
> 
> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> ---
> 
> Hopefully someone can give me some advice about cache flush. It
> confused me that why only 1 MiB is flushed from KERNEL_START on
> Book3S. Is there a need to flush L2 cache if I have already flushed
> L1 cache? If yes, how about L3 cache? Cache levels are different
> in cores, the instruction sets may also be different.
> 
>  1 files changed, 62 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/swsusp_asm64.S
> b/arch/powerpc/kernel/swsusp_asm64.S
> index 86ac1d9..608e4ceb 100644
> --- a/arch/powerpc/kernel/swsusp_asm64.S
> +++ b/arch/powerpc/kernel/swsusp_asm64.S
> @@ -46,10 +46,29 @@
>  #define SL_r29		0xe8
>  #define SL_r30		0xf0
>  #define SL_r31		0xf8
> -#define SL_SIZE		SL_r31+8
> +#define SL_SPRG0	0x100
> +#define SL_SPRG1	0x108
> +#define SL_SPRG2	0x110
> +#define SL_SPRG3	0x118
> +#define SL_SPRG4	0x120
> +#define SL_SPRG5	0x128
> +#define SL_SPRG6	0x130
> +#define SL_SPRG7	0x138
> +#define SL_TCR		0x140
> +#define SL_SIZE		SL_TCR+8
> 
>  /* these macros rely on the save area being
>   * pointed to by r11 */
> +
> +#define SAVE_SPR(register)		\
> +	mfspr	r0,SPRN_##register	;\
> +	std	r0,SL_##register(r11)
> +#define RESTORE_SPR(register)		\
> +	ld	r0,SL_##register(r11)	;\
> +	mtspr	SPRN_##register,r0
> +#define RESTORE_SPRG(n)			\
> +	ld	r0,SL_SPRG##n(r11)	;\
> +	mtsprg	n,r0
>  #define SAVE_SPECIAL(special)		\
>  	mf##special	r0		;\
>  	std	r0, SL_##special(r11)
> @@ -103,8 +122,21 @@ _GLOBAL(swsusp_arch_suspend)
>  	SAVE_REGISTER(r30)
>  	SAVE_REGISTER(r31)
>  	SAVE_SPECIAL(MSR)
> -	SAVE_SPECIAL(SDR1)
>  	SAVE_SPECIAL(XER)
> +#ifdef CONFIG_PPC_BOOK3S_64
> +	SAVE_SPECIAL(SDR1)
> +#else
> +	SAVE_SPR(TCR)
> +	/* Save SPRGs */
> +	SAVE_SPR(SPRG0)
> +	SAVE_SPR(SPRG1)
> +	SAVE_SPR(SPRG2)
> +	SAVE_SPR(SPRG3)
> +	SAVE_SPR(SPRG4)
> +	SAVE_SPR(SPRG5)
> +	SAVE_SPR(SPRG6)
> +	SAVE_SPR(SPRG7)
> +#endif
> 
>  	/* we push the stack up 128 bytes but don't store the
>  	 * stack pointer on the stack like a real stackframe */
> @@ -151,6 +183,7 @@ copy_page_loop:
>  	bne+	copyloop
>  nothing_to_copy:
> 
> +#ifdef CONFIG_PPC_BOOK3S_64
>  	/* flush caches */
>  	lis	r3, 0x10
>  	mtctr	r3
> @@ -167,6 +200,7 @@ nothing_to_copy:
>  	sync
> 
>  	tlbia
> +#endif
> 
>  	ld	r11,swsusp_save_area_ptr@toc(r2)
> 
> @@ -208,16 +242,42 @@ nothing_to_copy:
>  	RESTORE_REGISTER(r29)
>  	RESTORE_REGISTER(r30)
>  	RESTORE_REGISTER(r31)
> +
> +#ifdef CONFIG_PPC_BOOK3S_64
>  	/* can't use RESTORE_SPECIAL(MSR) */
>  	ld	r0, SL_MSR(r11)
>  	mtmsrd	r0, 0
>  	RESTORE_SPECIAL(SDR1)
> +#else
> +	/* Save SPRGs */
> +	RESTORE_SPRG(0)
> +	RESTORE_SPRG(1)
> +	RESTORE_SPRG(2)
> +	RESTORE_SPRG(3)
> +	RESTORE_SPRG(4)
> +	RESTORE_SPRG(5)
> +	RESTORE_SPRG(6)
> +	RESTORE_SPRG(7)
> +
> +	RESTORE_SPECIAL(MSR)
> +
> +	/* Restore TCR and clear any pending bits in TSR. */
> +	RESTORE_SPR(TCR)
> +	lis	r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
> +	mtspr	SPRN_TSR,r0
> +
> +	/* Kick decrementer */
> +	li	r0,1
> +	mtdec	r0
> +#endif
>  	RESTORE_SPECIAL(XER)
> 
>  	sync
> 
>  	addi	r1,r1,-128
> +#ifdef CONFIG_PPC_BOOK3S_64
>  	bl	slb_flush_and_rebolt
> +#endif
>  	bl	do_after_copyback
>  	addi	r1,r1,128
> 
> --
> 1.7.5.1
Johannes Berg - Feb. 22, 2013, 9:08 a.m.
Hi,

> > Subject: [RFC][PATCH] powerpc: add Book E support to 64-bit hibernation

> Any thoughts about this patch?

Heh, honestly, no. I know nothing about Book E, and it's too long ago
that I wrote (some of) the 64-bit hibernation code.

johannes
Wang Dongsheng-B40534 - Feb. 22, 2013, 9:50 a.m.
> -----Original Message-----
> From: Johannes Berg [mailto:johannes@sipsolutions.net]
> Sent: Friday, February 22, 2013 5:09 PM
> To: Wang Dongsheng-B40534
> Cc: benh@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; Wood Scott-
> B07421; Li Yang-R58472; Zhao Chenhui-B35336
> Subject: Re: [RFC][PATCH] powerpc: add Book E support to 64-bit
> hibernation
> 
> Hi,
> 
> > > Subject: [RFC][PATCH] powerpc: add Book E support to 64-bit
> > > hibernation
> 
> > Any thoughts about this patch?
> 
> Heh, honestly, no. I know nothing about Book E, and it's too long ago
> that I wrote (some of) the 64-bit hibernation code.
> 
Thanks for your feedback.

Could you give me some advice about cache flush. It confused me that why
only 1 MiB is flushed from KERNEL_START on Powermac G5.

On FSL Book E(e500 family), Even if I don't flash cache, the work is
also normal(Dcaches are kept coherent by hardware, and icaches are kept
coherent by software). But I still worry about caches. Is there a need
to flush L2 cache if I have already flushed L1 cache? 
Or on Powermac G5, flush caches is a general way?

Powermac G5 Codes:
        /* flush caches */
        lis     r3, 0x10
        mtctr   r3
        li      r3, 0
        ori     r3, r3, CONFIG_KERNEL_START>>48
        li      r0, 48
        sld     r3, r3, r0
        li      r0, 0
1:
        dcbf    r0,r3
        addi    r3,r3,0x20
        bdnz    1b

        sync

        tlbia

> johannes
>

Patch

diff --git a/arch/powerpc/kernel/swsusp_asm64.S b/arch/powerpc/kernel/swsusp_asm64.S
index 86ac1d9..608e4ceb 100644
--- a/arch/powerpc/kernel/swsusp_asm64.S
+++ b/arch/powerpc/kernel/swsusp_asm64.S
@@ -46,10 +46,29 @@ 
 #define SL_r29		0xe8
 #define SL_r30		0xf0
 #define SL_r31		0xf8
-#define SL_SIZE		SL_r31+8
+#define SL_SPRG0	0x100
+#define SL_SPRG1	0x108
+#define SL_SPRG2	0x110
+#define SL_SPRG3	0x118
+#define SL_SPRG4	0x120
+#define SL_SPRG5	0x128
+#define SL_SPRG6	0x130
+#define SL_SPRG7	0x138
+#define SL_TCR		0x140
+#define SL_SIZE		SL_TCR+8
 
 /* these macros rely on the save area being
  * pointed to by r11 */
+
+#define SAVE_SPR(register)		\
+	mfspr	r0,SPRN_##register	;\
+	std	r0,SL_##register(r11)
+#define RESTORE_SPR(register)		\
+	ld	r0,SL_##register(r11)	;\
+	mtspr	SPRN_##register,r0
+#define RESTORE_SPRG(n)			\
+	ld	r0,SL_SPRG##n(r11)	;\
+	mtsprg	n,r0
 #define SAVE_SPECIAL(special)		\
 	mf##special	r0		;\
 	std	r0, SL_##special(r11)
@@ -103,8 +122,21 @@  _GLOBAL(swsusp_arch_suspend)
 	SAVE_REGISTER(r30)
 	SAVE_REGISTER(r31)
 	SAVE_SPECIAL(MSR)
-	SAVE_SPECIAL(SDR1)
 	SAVE_SPECIAL(XER)
+#ifdef CONFIG_PPC_BOOK3S_64
+	SAVE_SPECIAL(SDR1)
+#else
+	SAVE_SPR(TCR)
+	/* Save SPRGs */
+	SAVE_SPR(SPRG0)
+	SAVE_SPR(SPRG1)
+	SAVE_SPR(SPRG2)
+	SAVE_SPR(SPRG3)
+	SAVE_SPR(SPRG4)
+	SAVE_SPR(SPRG5)
+	SAVE_SPR(SPRG6)
+	SAVE_SPR(SPRG7)
+#endif
 
 	/* we push the stack up 128 bytes but don't store the
 	 * stack pointer on the stack like a real stackframe */
@@ -151,6 +183,7 @@  copy_page_loop:
 	bne+	copyloop
 nothing_to_copy:
 
+#ifdef CONFIG_PPC_BOOK3S_64
 	/* flush caches */
 	lis	r3, 0x10
 	mtctr	r3
@@ -167,6 +200,7 @@  nothing_to_copy:
 	sync
 
 	tlbia
+#endif
 
 	ld	r11,swsusp_save_area_ptr@toc(r2)
 
@@ -208,16 +242,42 @@  nothing_to_copy:
 	RESTORE_REGISTER(r29)
 	RESTORE_REGISTER(r30)
 	RESTORE_REGISTER(r31)
+
+#ifdef CONFIG_PPC_BOOK3S_64
 	/* can't use RESTORE_SPECIAL(MSR) */
 	ld	r0, SL_MSR(r11)
 	mtmsrd	r0, 0
 	RESTORE_SPECIAL(SDR1)
+#else
+	/* Save SPRGs */
+	RESTORE_SPRG(0)
+	RESTORE_SPRG(1)
+	RESTORE_SPRG(2)
+	RESTORE_SPRG(3)
+	RESTORE_SPRG(4)
+	RESTORE_SPRG(5)
+	RESTORE_SPRG(6)
+	RESTORE_SPRG(7)
+
+	RESTORE_SPECIAL(MSR)
+
+	/* Restore TCR and clear any pending bits in TSR. */
+	RESTORE_SPR(TCR)
+	lis	r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
+	mtspr	SPRN_TSR,r0
+
+	/* Kick decrementer */
+	li	r0,1
+	mtdec	r0
+#endif
 	RESTORE_SPECIAL(XER)
 
 	sync
 
 	addi	r1,r1,-128
+#ifdef CONFIG_PPC_BOOK3S_64
 	bl	slb_flush_and_rebolt
+#endif
 	bl	do_after_copyback
 	addi	r1,r1,128