From patchwork Wed Feb 6 23:26:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 218800 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DB9C72C02F8 for ; Thu, 7 Feb 2013 10:27:30 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E40E74A12D; Thu, 7 Feb 2013 00:27:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id o-QYef7hTxVt; Thu, 7 Feb 2013 00:27:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF7124A112; Thu, 7 Feb 2013 00:27:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DCCA64A0BF for ; Thu, 7 Feb 2013 00:27:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4lXGubbCvhNV for ; Thu, 7 Feb 2013 00:27:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f45.google.com (mail-pa0-f45.google.com [209.85.220.45]) by theia.denx.de (Postfix) with ESMTPS id 83C204A0C1 for ; Thu, 7 Feb 2013 00:27:13 +0100 (CET) Received: by mail-pa0-f45.google.com with SMTP id kl14so1061732pab.32 for ; Wed, 06 Feb 2013 15:27:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=RRW1JbPojrAncSRR5URmFob6GOpkH1wlbxYNnBM+r90=; b=xeyHntNKWS/N0+1xNUeV1ijh8fV+oWyz4qP/kRi7Vr4FHXaXO3CD6cXRTamTq8YkW4 oaSPpuiIrMNLSve9687WbBc5eoJCWY1vNat9IwPvy9ssPimJH8SJuZeJlErBHhbPlRa/ bEK+aFJ7yZhE963ccKjBEcqvdbkQ3WldsuydHGUGiFFo6uXBDCkv+zZ8kHkzpUJIe9y9 LdOfljszF3X1QyIhSSk2bIN4hm8X8oy2wCroUV7+rmGmgvZUpuP+uMOHdvg0Nns0p9N5 XEMqDnZF0K+HozajDqq7vLkm4H7sRV10vBkdGvYbW+VyTFk8pJLkxHgwZL+XMDNdAca0 +pEg== X-Received: by 10.66.81.7 with SMTP id v7mr5299420pax.69.1360193232163; Wed, 06 Feb 2013 15:27:12 -0800 (PST) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id b3sm38402644pax.14.2013.02.06.15.27.09 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 06 Feb 2013 15:27:11 -0800 (PST) From: Tom Warren To: u-boot@lists.denx.de Date: Wed, 6 Feb 2013 16:26:46 -0700 Message-Id: <1360193208-16055-2-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1360193208-16055-1-git-send-email-twarren@nvidia.com> References: <1360193208-16055-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: twarren.nvidia@gmail.com, swarren@nvidia.com, Tom Warren , hs@denx.de Subject: [U-Boot] [PATCH v2 1/3] Tegra: I2C: Add T114 clock support to tegra_i2c driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de T114 has a slightly different I2C clock, with a new divisor for standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3% on my Saleae Logic analyzer. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren Acked-by: Laxman Dewangan --- v2: new arch/arm/include/asm/arch-tegra/tegra_i2c.h | 6 ++++++ drivers/i2c/tegra_i2c.c | 22 +++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 2650744..853e59b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -105,6 +105,7 @@ struct i2c_ctlr { u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ u32 reserved_2[4]; /* 40: */ struct i2c_control control; /* 50 ~ 68 */ + u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ }; /* bit fields definitions for IO Packet Header 1 format */ @@ -154,6 +155,11 @@ struct i2c_ctlr { #define I2C_INT_ARBITRATION_LOST_SHIFT 2 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) +/* I2C_CLK_DIVISOR_REGISTER */ +#define CLK_DIV_STD_FAST_MODE 0x19 +#define CLK_DIV_HS_MODE 1 +#define CLK_MULT_STD_FAST_MODE 8 + /** * Returns the bus number of the DVC controller * diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index efc77fa..0558648 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -88,7 +88,27 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * 16 to get the right frequency. */ clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, - i2c_bus->speed * 2 * 8); + i2c_bus->speed * 2 * 8); +#if defined(CONFIG_TEGRA114) + /* + * T114 I2C went to a single clock source for standard/fast and + * HS clock speeds. The new clock rate setting calculation is: + * SCL = CLK_SOURCE.I2C / + * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * + * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). + * + * NOTE: We do this here, after the initial clock/pll start, + * because if we read the clk_div reg before the controller + * is running, we hang, and we need it for the new calc. + */ + int clk_div_std_fast_mode = readl(&i2c_bus->regs->clk_div) >> 16; + debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, + clk_div_std_fast_mode); + + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + CLK_MULT_STD_FAST_MODE * (clk_div_std_fast_mode+1) * + i2c_bus->speed * 2); +#endif /* T114 */ /* Reset I2C controller. */ i2c_reset_controller(i2c_bus);