From patchwork Wed Feb 6 17:38:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 218706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E8C8E2C029D for ; Thu, 7 Feb 2013 04:38:35 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752003Ab3BFRif (ORCPT ); Wed, 6 Feb 2013 12:38:35 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:14273 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755392Ab3BFRie (ORCPT ); Wed, 6 Feb 2013 12:38:34 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Wed, 06 Feb 2013 09:43:02 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 06 Feb 2013 09:38:02 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 06 Feb 2013 09:38:02 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.297.1; Wed, 6 Feb 2013 09:38:29 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Wed, 06 Feb 2013 09:39:47 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r16HcQqt028276; Wed, 6 Feb 2013 09:38:27 -0800 (PST) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu Subject: [PATCH 1/1] iommu/tegra: smmu: Fix incorrect mask for regbase Date: Wed, 6 Feb 2013 19:38:15 +0200 Message-ID: <1360172295-21500-1-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This fixes kernel crash because of BUG() in register address validation. Signed-off-by: Hiroshi Doyu Tested-by: Stephen Warren --- Verified with Tegra 114 based Dalmore board --- drivers/iommu/tegra-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 4d11069..05a8ddb 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -1192,7 +1192,7 @@ static int tegra_smmu_probe(struct platform_device *pdev) smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1; } /* Same as "mc" 1st regiter block start address */ - smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & ~PAGE_MASK); + smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK); err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size); if (err)