From patchwork Wed Feb 6 09:45:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 218526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E30EB2C0099 for ; Wed, 6 Feb 2013 21:13:33 +1100 (EST) Received: from localhost ([::1]:57581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U320R-0005TY-Uf for incoming@patchwork.ozlabs.org; Wed, 06 Feb 2013 05:13:31 -0500 Received: from eggs.gnu.org ([208.118.235.92]:42183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U320I-0005T3-UG for qemu-devel@nongnu.org; Wed, 06 Feb 2013 05:13:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U320E-00060Z-QJ for qemu-devel@nongnu.org; Wed, 06 Feb 2013 05:13:22 -0500 Received: from mail-ia0-x22c.google.com ([2607:f8b0:4001:c02::22c]:53049) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U320E-00060R-JM for qemu-devel@nongnu.org; Wed, 06 Feb 2013 05:13:18 -0500 Received: by mail-ia0-f172.google.com with SMTP id u8so1365106iag.3 for ; Wed, 06 Feb 2013 02:13:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=la4NDOkasDwqMzJgW0fUnuX4WOVZ+8yoWHHfLCPscqQ=; b=qkLrVpEURMx7wdOkn4l0RveL86ws7CAGGIEgpl8u42FS7tD1qQ2WjpiWDqi/Aae6/+ VLFkEa/SJ6Q9FM+kIhiN2ingSETtgBNunLjKRC6o3aeXKQO4qN2D1mgtsJrH2l5hPHQO MUNH89W83fzptdcAoAXu/vCv0WxrlnXztTF+wxkD56m0Joo1SHWq0AroZPVidOX50sLl 5bBdWZhtnCh8fW0xaicdj9jFmYisL1KzonmQXRehgKx9Bv5J7S20PCS3lmqo9K+6OoLC 1kpJBuc+iEdNlSWyqxLQeQkXUp1B2KJ+gU2PfKR94N0SicTBESDlFNxFiRTaCUfeDPpv fn/g== X-Received: by 10.42.51.207 with SMTP id f15mr27490870icg.16.1360143998775; Wed, 06 Feb 2013 01:46:38 -0800 (PST) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPS id hg2sm2671279igc.3.2013.02.06.01.46.35 (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Wed, 06 Feb 2013 01:46:38 -0800 (PST) From: Kuo-Jung Su To: qemu-devel@nongnu.org Date: Wed, 6 Feb 2013 17:45:07 +0800 Message-Id: <1360143925-10800-4-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360143925-10800-1-git-send-email-dantesu@gmail.com> References: <1360143925-10800-1-git-send-email-dantesu@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c02::22c Cc: Peter Maydell , i.mitsyanko@samsung.com, Blue Swirl , Paul Brook , Kuo-Jung Su , Andreas , fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v3 03/20] arm: add Faraday FTAHBC020 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Kuo-Jung Su It's used to perform AHB remap and also QEMU RAM initialization when SDRAM is initialized before AHB remap process activated. Signed-off-by: Kuo-Jung Su --- hw/arm/Makefile.objs | 1 + hw/arm/faraday_a369.c | 6 ++ hw/arm/ftahbc020.c | 185 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 hw/arm/ftahbc020.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 02d1a7b..5825c63 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -35,3 +35,4 @@ obj-$(CONFIG_FDT) += ../device_tree.o obj-y := $(addprefix ../,$(obj-y)) obj-y += faraday_a360.o faraday_a360_pmu.o obj-y += faraday_a369.o faraday_a369_scu.o faraday_a369_keypad.o +obj-y += ftahbc020.o diff --git a/hw/arm/faraday_a369.c b/hw/arm/faraday_a369.c index e32dc7f..ae6c445 100644 --- a/hw/arm/faraday_a369.c +++ b/hw/arm/faraday_a369.c @@ -54,6 +54,12 @@ a369_device_init(A369State *s) /* ftkbc010 */ sysbus_create_simple("a369.keypad", 0x92f00000, NULL); + + /* ftahbc020 */ + s->ahbc = qdev_create(NULL, "ftahbc020"); + qdev_prop_set_ptr(s->ahbc, "mach", s); + qdev_init_nofail(s->ahbc); + sysbus_mmio_map(SYS_BUS_DEVICE(s->ahbc), 0, 0x94000000); } static void diff --git a/hw/arm/ftahbc020.c b/hw/arm/ftahbc020.c new file mode 100644 index 0000000..d68676c --- /dev/null +++ b/hw/arm/ftahbc020.c @@ -0,0 +1,185 @@ +/* + * Faraday AHB controller + * + * Copyright (c) 2012 Faraday Technology + * Written by Dante Su + * + * This code is licensed under GNU GPL v2+ + */ + +#include +#include +#include +#include +#include +#include + +#include "faraday.h" + +#define REG_SLAVE(n) (n * 4) /* Slave device config (base & size) */ +#define REG_PRIR 0x80 /* Priority register */ +#define REG_IDLECR 0x84 /* IDLE count register */ +#define REG_CR 0x88 /* Control register */ +#define REG_REVR 0x8c /* Revision register */ + +#define TYPE_FTAHBC020 "ftahbc020" + +typedef struct Ftahbc020State { + SysBusDevice busdev; + MemoryRegion iomem; + void *mach; + + /* HW register cache */ + uint32_t slave4; + uint32_t slave6; + uint32_t cr; +} Ftahbc020State; + +#define FTAHBC020(obj) \ + OBJECT_CHECK(Ftahbc020State, obj, TYPE_FTAHBC020) + +static uint64_t +ftahbc020_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + Ftahbc020State *s = FTAHBC020(opaque); + uint64_t ret = 0; + + switch (addr) { + case REG_SLAVE(4): + ret = s->slave4; + break; + case REG_SLAVE(6): + ret = s->slave6; + break; + case REG_CR: + ret = s->cr; + break; + case REG_REVR: + ret = 0x00010301; + break; + } + + return ret; +} + +static void +ftahbc020_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + Ftahbc020State *s = FTAHBC020(opaque); + FaradayMachState *mach = s->mach; + uint32_t base; + + if (!mach) { + hw_error("ftahbc020: mach is not yet registered!\n"); + exit(1); + } + + switch (addr) { + case REG_CR: + s->cr = (uint32_t)val; + if (!mach->ahb_remapped && (s->cr & 0x01)) { + /* Remap AHB slave 4 (ROM) & slave 6 (RAM) */ + /* 1. Remap ROM to (0x00000000 + size of RAM) */ + base = (1 << ((s->slave6 >> 16) & 0x0f)) << 20; + sysbus_mmio_map(SYS_BUS_DEVICE(mach->rom), 0, base); + /* 2. Update slave4(ROM) & slave6(RAM) */ + s->slave4 = base | (s->slave4 & 0x000fffff); + s->slave6 = s->slave6 & 0x000fffff; + /* 3. Update SDRAM map if it has been initialized. */ + if (mach->ddr_inited) { + memory_region_del_subregion(mach->as, mach->ram_alias); + memory_region_add_subregion(mach->as, 0, mach->ram); + } + mach->ahb_remapped = 1; + } + break; + } +} + +static const MemoryRegionOps ftahbc020_mem_ops = { + .read = ftahbc020_mem_read, + .write = ftahbc020_mem_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void ftahbc020_reset(DeviceState *ds) +{ + SysBusDevice *busdev = SYS_BUS_DEVICE(ds); + Ftahbc020State *s = FTAHBC020(FROM_SYSBUS(Ftahbc020State, busdev)); + FaradayMachState *mach = s->mach; + + if (!mach) { + hw_error("ftahbc020: mach is not yet initialized!\n"); + exit(1); + } + + if (mach->ahb_remapped) { + sysbus_mmio_map(SYS_BUS_DEVICE(mach->rom), 0, 0x00000000); + mach->ahb_remapped = 0; + } + + s->cr = 0; + s->slave4 = mach->ahb_slave4; + s->slave6 = mach->ahb_slave6; + + if (s->slave4 == 0 || s->slave6 == 0) { + hw_error("ftahbc020: slave 4 or 6 is not yet initialized!\n"); + exit(1); + } +} + +static int ftahbc020_init(SysBusDevice *dev) +{ + Ftahbc020State *s = FTAHBC020(FROM_SYSBUS(Ftahbc020State, dev)); + + memory_region_init_io(&s->iomem, + &ftahbc020_mem_ops, + s, + TYPE_FTAHBC020, + 0x1000); + sysbus_init_mmio(dev, &s->iomem); + return 0; +} + +static Property ftahbc020_properties[] = { + DEFINE_PROP_PTR("mach", Ftahbc020State, mach), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_ftahbc020 = { + .name = TYPE_FTAHBC020, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(cr, Ftahbc020State), + VMSTATE_END_OF_LIST(), + } +}; + +static void ftahbc020_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + k->init = ftahbc020_init; + dc->desc = TYPE_FTAHBC020; + dc->vmsd = &vmstate_ftahbc020; + dc->props = ftahbc020_properties; + dc->reset = ftahbc020_reset; + dc->no_user = 1; +} + +static const TypeInfo ftahbc020_info = { + .name = TYPE_FTAHBC020, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Ftahbc020State), + .class_init = ftahbc020_class_init, +}; + +static void ftahbc020_register_types(void) +{ + type_register_static(&ftahbc020_info); +} + +type_init(ftahbc020_register_types)