From patchwork Wed Feb 6 09:45:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 218522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BB6FE2C02C1 for ; Wed, 6 Feb 2013 21:03:14 +1100 (EST) Received: from localhost ([::1]:40230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U31bS-0003DF-Eh for incoming@patchwork.ozlabs.org; Wed, 06 Feb 2013 04:47:42 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35305) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U31b8-0002yZ-Vr for qemu-devel@nongnu.org; Wed, 06 Feb 2013 04:47:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U31b5-0007A1-7X for qemu-devel@nongnu.org; Wed, 06 Feb 2013 04:47:22 -0500 Received: from mail-ie0-x234.google.com ([2607:f8b0:4001:c03::234]:46722) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U31b5-000796-1M for qemu-devel@nongnu.org; Wed, 06 Feb 2013 04:47:19 -0500 Received: by mail-ie0-f180.google.com with SMTP id bn7so1607641ieb.25 for ; Wed, 06 Feb 2013 01:47:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=JRGY1sEitLfvBTMEHPvpYuCE6HfmWOM8UEWrfVBk7aE=; b=w/A6dZqzxjlqUrx6YD9My3PE8vU3W3tUJi2A22p/MZiGZi62Uf75gGWWvq6NrxRIxv h3JeX8/JOtqs2uLF3AXpHB8M/MbjWLpq7baSqkYqL+Zedz8Qz2m85usbKfTOkVIyXGEx Q72iyvN6hMxnwtF8PWU5I/2fWSxAlQxWOw10QaQb2G4KbDGX8UowjKra1TbfXJFfnJ/Q r3u4KIOyzTpX5rjXuQgifZdrk1Fm1UTJJHQyEmrvbNlc72enzxDijkfafwkV1+iZCE+r g4nDUju1iwtheLjNe0ORk9pTRAchkGZvuyeHtGH+06vheiWhK/FtyrdJhKg9MYkAr1ud hR7Q== X-Received: by 10.50.195.132 with SMTP id ie4mr4517680igc.81.1360144038425; Wed, 06 Feb 2013 01:47:18 -0800 (PST) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPS id hg2sm2671279igc.3.2013.02.06.01.47.15 (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Wed, 06 Feb 2013 01:47:17 -0800 (PST) From: Kuo-Jung Su To: qemu-devel@nongnu.org Date: Wed, 6 Feb 2013 17:45:16 +0800 Message-Id: <1360143925-10800-13-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360143925-10800-1-git-send-email-dantesu@gmail.com> References: <1360143925-10800-1-git-send-email-dantesu@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c03::234 Cc: Peter Maydell , i.mitsyanko@samsung.com, Blue Swirl , Paul Brook , Kuo-Jung Su , Andreas , fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v3 12/20] arm: add Faraday FTI2C010 I2C controller support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Kuo-Jung Su The FTI2C010 is an I2C master controller. Signed-off-by: Kuo-Jung Su --- hw/arm/Makefile.objs | 1 + hw/arm/faraday_a360.c | 6 ++ hw/arm/faraday_a369.c | 6 ++ hw/arm/fti2c010.c | 206 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/arm/fti2c010.h | 62 +++++++++++++++ 5 files changed, 281 insertions(+) create mode 100644 hw/arm/fti2c010.c create mode 100644 hw/arm/fti2c010.h diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 1ef36df..4fcd1ab 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -44,3 +44,4 @@ obj-y += ftwdt010.o obj-y += ftrtc011.o obj-y += ftdmac020.o obj-y += ftapbbrg020.o +obj-y += fti2c010.o diff --git a/hw/arm/faraday_a360.c b/hw/arm/faraday_a360.c index dff28b1..3116563 100644 --- a/hw/arm/faraday_a360.c +++ b/hw/arm/faraday_a360.c @@ -80,6 +80,12 @@ a360_device_init(A360State *s) /* ftapbbrg020 */ s->pdma[0] = sysbus_create_simple("ftapbbrg020", 0x90500000, pic[24]); + + /* fti2c010 */ + ds = sysbus_create_simple("fti2c010", 0x98A00000, pic[3]); + s->i2c[0] = (i2c_bus *)qdev_get_child_bus(ds, "i2c"); + ds = sysbus_create_simple("fti2c010", 0x98C00000, pic[22]); + s->i2c[1] = (i2c_bus *)qdev_get_child_bus(ds, "i2c"); } static void diff --git a/hw/arm/faraday_a369.c b/hw/arm/faraday_a369.c index 99e5f99..a58cae7 100644 --- a/hw/arm/faraday_a369.c +++ b/hw/arm/faraday_a369.c @@ -124,6 +124,12 @@ a369_device_init(A369State *s) /* ftapbbrg020 */ s->pdma[0] = sysbus_create_simple("ftapbbrg020", 0x90f00000, pic[14]); + + /* fti2c010 */ + ds = sysbus_create_simple("fti2c010", 0x92900000, pic[51]); + s->i2c[0] = (i2c_bus *)qdev_get_child_bus(ds, "i2c"); + ds = sysbus_create_simple("fti2c010", 0x92A00000, pic[52]); + s->i2c[1] = (i2c_bus *)qdev_get_child_bus(ds, "i2c"); } static void diff --git a/hw/arm/fti2c010.c b/hw/arm/fti2c010.c new file mode 100644 index 0000000..7690d77 --- /dev/null +++ b/hw/arm/fti2c010.c @@ -0,0 +1,206 @@ +/* + * QEMU model of the FTI2C010 Controller + * + * Copyright (C) 2012 Faraday Technology + * Written by Dante Su + * + * This file is licensed under GNU GPL v2+. + */ + +#include +#include +#include + +#include "fti2c010.h" + +#define I2C_RD 1 +#define I2C_WR 0 + +#define TYPE_FTI2C010 "fti2c010" + +typedef struct Fti2c010State { + SysBusDevice busdev; + MemoryRegion mmio; + + qemu_irq irq; + i2c_bus *bus; + + uint32_t cr; + uint32_t sr; + uint32_t cdr; + uint32_t dr; + uint32_t tgsr; + + uint8_t recv; /* I2C RD = 1; I2C WR = 0 */ + uint8_t addr; /* 7-bits device address */ + +} Fti2c010State; + +#define FTI2C010(obj) \ + OBJECT_CHECK(Fti2c010State, obj, TYPE_FTI2C010) + +static uint64_t fti2c010_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + Fti2c010State *s = FTI2C010(opaque); + uint32_t rc = 0; + + switch (addr) { + case REG_CR: + return s->cr; + case REG_SR: + rc = s->sr | (i2c_bus_busy(s->bus) ? SR_BB : 0); + s->sr &= 0xfffff00f; + qemu_set_irq(s->irq, 0); + break; + case REG_CDR: + return s->cdr; + case REG_DR: + return s->dr; + case REG_TGSR: + return s->tgsr; + case REG_BMR: + return 0x00000003; + case 0x30: /* revision register */ + return 0x00011000; + default: + break; + } + + return rc; +} + +static void fti2c010_mem_write(void *opaque, + hwaddr addr, + uint64_t val, + unsigned size) +{ + Fti2c010State *s = FTI2C010(opaque); + + switch (addr) { + case REG_CR: + s->cr = (uint32_t)val; + if (s->cr & CR_I2CRST) { + s->dr = 0; + s->sr = 0; + } else if ((s->cr & (CR_MASTER_EN | CR_TBEN)) + == (CR_MASTER_EN | CR_TBEN)) { + s->sr &= ~SR_ACK; + if (s->cr & CR_START) { + s->recv = (s->dr & I2C_RD) ? 1 : 0; + s->addr = (s->dr >> 1) & 0x7f; + if (i2c_start_transfer(s->bus, s->addr, s->recv) == 0) { + s->sr |= SR_DT | SR_ACK; + } else { + s->sr &= ~SR_DT; + } + } else { + if (s->recv) { + s->dr = i2c_recv(s->bus); + s->sr |= SR_DR; + } else { + i2c_send(s->bus, (uint8_t)s->dr); + s->sr |= SR_DT; + } + if (s->cr & CR_NACK) { + i2c_nack(s->bus); + } + s->sr |= SR_ACK; + if (s->cr & CR_STOP) { + i2c_end_transfer(s->bus); + } + } + } + s->cr &= 0xffffff7e; /* clear TB_EN, I2C_RST */ + if ((s->sr >> 4) & (s->cr >> 8)) { + qemu_set_irq(s->irq, 1); + } + break; + case REG_CDR: + s->cdr = (uint32_t)val; + break; + case REG_DR: + s->dr = (uint32_t)val & 0xff; + break; + case REG_TGSR: + s->tgsr = (uint32_t)val; + break; + default: + break; + } +} + +static const MemoryRegionOps fti2c010_ops = { + .read = fti2c010_mem_read, + .write = fti2c010_mem_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void fti2c010_reset(DeviceState *ds) +{ + SysBusDevice *busdev = SYS_BUS_DEVICE(ds); + Fti2c010State *s = FTI2C010(FROM_SYSBUS(Fti2c010State, busdev)); + + s->cr = 0; + s->sr = 0; + s->cdr = 0; + s->tgsr = 0x00000401; + + qemu_set_irq(s->irq, 0); +} + +static int fti2c010_init(SysBusDevice *dev) +{ + Fti2c010State *s = FTI2C010(FROM_SYSBUS(Fti2c010State, dev)); + + s->bus = i2c_init_bus(&dev->qdev, "i2c"); + + memory_region_init_io(&s->mmio, &fti2c010_ops, s, TYPE_FTI2C010, 0x1000); + sysbus_init_mmio(dev, &s->mmio); + sysbus_init_irq(dev, &s->irq); + + return 0; +} + +static const VMStateDescription vmstate_fti2c010 = { + .name = TYPE_FTI2C010, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(cr, Fti2c010State), + VMSTATE_UINT32(sr, Fti2c010State), + VMSTATE_UINT32(cdr, Fti2c010State), + VMSTATE_UINT32(dr, Fti2c010State), + VMSTATE_UINT32(tgsr, Fti2c010State), + VMSTATE_END_OF_LIST() + } +}; + +static void fti2c010_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + k->init = fti2c010_init; + dc->vmsd = &vmstate_fti2c010; + dc->reset = fti2c010_reset; + dc->no_user = 1; +} + +static const TypeInfo fti2c010_info = { + .name = TYPE_FTI2C010, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Fti2c010State), + .class_init = fti2c010_class_init, +}; + +static void fti2c010_register_types(void) +{ + type_register_static(&fti2c010_info); +} + +type_init(fti2c010_register_types) diff --git a/hw/arm/fti2c010.h b/hw/arm/fti2c010.h new file mode 100644 index 0000000..10df34d --- /dev/null +++ b/hw/arm/fti2c010.h @@ -0,0 +1,62 @@ +/* + * QEMU model of the FTI2C010 Controller + * + * Copyright (C) 2012 Faraday Technology + * Written by Dante Su + * + * This file is licensed under GNU GPL v2+. + */ + +#ifndef HW_ARM_FTI2C010_H +#define HW_ARM_FTI2C010_H + +/* + * FTI2C010 registers + */ +#define REG_CR 0x00 +#define REG_SR 0x04 +#define REG_CDR 0x08 +#define REG_DR 0x0C +#define REG_SAR 0x10 +#define REG_TGSR 0x14 +#define REG_BMR 0x18 + +/* + * REG_CR + */ +#define CR_STARTIEN 0x4000 /* start condition */ +#define CR_ALIEN 0x2000 /* Arbitration lose */ +#define CR_SAMIEN 0x1000 /* slave address match */ +#define CR_STOPIEN 0x800 /* stop condition */ +#define CR_BERRIEN 0x400 /* non ACK response */ +#define CR_DRIEN 0x200 /* data receive */ +#define CR_DTIEN 0x100 /* data transmit */ +#define CR_TBEN 0x80 /* transfer byte enable */ +#define CR_NACK 0x40 +#define CR_STOP 0x20 /* stop */ +#define CR_START 0x10 /* start */ +#define CR_GCEN 0x8 /* general call */ +#define CR_SCLEN 0x4 /* enable clock */ +#define CR_I2CEN 0x2 /* enable I2C */ +#define CR_I2CRST 0x1 /* reset I2C */ +#define CR_MASTER_INTR (CR_ALIEN | CR_BERRIEN | CR_DRIEN | CR_DTIEN) +#define CR_MASTER_EN (CR_SCLEN | CR_I2CEN) +#define CR_MASTER_MODE (CR_MASTER_INTR | CR_MASTER_EN) + +/* + * REG_SR + */ +#define SR_START 0x800 +#define SR_AL 0x400 +#define SR_GC 0x200 +#define SR_SAM 0x100 +#define SR_STOP 0x80 +#define SR_BERR 0x40 +#define SR_DR 0x20 /* received one new data byte */ +#define SR_DT 0x10 /* trandmitted one data byte */ +#define SR_BB 0x8 /* set when i2c bus is busy */ +#define SR_I2CB 0x4 /* set when fti2c010 is busy */ +#define SR_ACK 0x2 +#define SR_RW 0x1 + +#endif /* EOF */