diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
old mode 100644
new mode 100755
index 0c3afcc..a76ff7b
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -306,6 +306,9 @@ static int nand_block_bad(struct mtd_info *mtd,
loff_t ofs, int getchip)
 
 	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 
+	if( chip->options & NAND_BB_LAST_PAGE )
+		ofs += (mtd->erasesize - mtd->writesize);
+
 	if (getchip) {
 		chipnr = (int)(ofs >> chip->chip_shift);
 
@@ -358,6 +361,9 @@ static int nand_default_block_markbad(struct
mtd_info *mtd, loff_t ofs)
 	if (chip->options & NAND_USE_FLASH_BBT)
 		ret = nand_update_bbt(mtd, ofs);
 	else {
+		if( chip->options & NAND_BB_LAST_PAGE )
+			ofs += (mtd->erasesize - mtd->writesize);
+
 		/* We write two bytes, so we dont have to mess with 16
bit
 		 * access
 		 */
@@ -2450,6 +2456,12 @@ static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info *mtd,
 	if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
 		chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
 
+	/* Check if the device is an MLC nand with alternative bb marker
location. 
+         * At this stage, I only know that this is the case for Samsung
and ST/Numonyx, 
+         * and is NOT the case for Micron */
+	if( (*maf_id == NAND_MFR_SAMSUNG || *maf_id == NAND_MFR_ST)  &&
((chip->cellinfo >> 2) & 0x3) != 0 )
+		chip->options |= NAND_BB_LAST_PAGE;
+
 	/* Check for AND chips with 4 page planes */
 	if (chip->options & NAND_4PAGE_ARRAY)
 		chip->erase_cmd = multi_erase_cmd;
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
old mode 100644
new mode 100755
index 55c23e5..4c2edcf
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -414,6 +414,9 @@ static int create_bbt(struct mtd_info *mtd, uint8_t
*buf,
 		from = (loff_t)startblock << (this->bbt_erase_shift -
1);
 	}
 
+	if( this->options & NAND_BB_LAST_PAGE )
+		from += (mtd->erasesize - (mtd->writesize * len));
+
 	for (i = startblock; i < numblocks;) {
 		int ret;
 
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
old mode 100644
new mode 100755
index db5b63d..dd7a6ae
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -166,7 +166,8 @@ typedef enum {
 #define NAND_NO_READRDY		0x00000100
 /* Chip does not allow subpage writes */
 #define NAND_NO_SUBPAGE_WRITE	0x00000200
-
+/* Chip holds bad-block marker in last page instead of first page (eg.
on samsung MLC) */
+#define NAND_BB_LAST_PAGE	0x00000400
 
 /* Options valid for Samsung large page devices */