From patchwork Mon Feb 4 14:36:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 217951 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2E7DF2C007C for ; Tue, 5 Feb 2013 01:36:26 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 410834A127; Mon, 4 Feb 2013 15:36:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CcaiUdZrGuI3; Mon, 4 Feb 2013 15:36:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 372E34A133; Mon, 4 Feb 2013 15:36:19 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 36C544A10D for ; Mon, 4 Feb 2013 15:36:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AkUFrF+iL8rf for ; Mon, 4 Feb 2013 15:36:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by theia.denx.de (Postfix) with ESMTPS id 3F04C4A0AF for ; Mon, 4 Feb 2013 15:36:11 +0100 (CET) Received: by mail-wi0-f177.google.com with SMTP id hm14so2977419wib.10 for ; Mon, 04 Feb 2013 06:36:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=DEGUn4Jw5eIjCdFToJL8TuwSE8sRqlOal79UMwvPcc4=; b=hE131Oz4rmQVjIvEGVsoqWRKk8PWJxgpPBonSg8uZiLQ5DMwx5OyYfeV0edjXuJKl1 OD563m8lf2Yt+KZ3U0uCdqiR2nBFKo+Lgt5TKXkt+M0XIdFMWs4GixNMeXxh7UpfQKIH KmoS8lAvUjnk/H6e7L303Ffn/E4f6C2u3iRiezhxITb4sVAbddFaATkKNirUXSkZnZIu Qh033tH9pWLo3XJn3Xbd7dAfiJa3+eBxI3JYsMz6ovNFA+z71Wt0GhcP2tu0+ZwuLWwa ulrYSyd4qQg72VN9c/87AVIP0brJHZVVLMFeidsjT9XmhPUtDU/dRPjeDBXBIqJ3qUF8 N+Dg== X-Received: by 10.180.83.227 with SMTP id t3mr10960030wiy.2.1359988571558; Mon, 04 Feb 2013 06:36:11 -0800 (PST) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPS id df2sm20347210wib.0.2013.02.04.06.36.10 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 04 Feb 2013 06:36:10 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Mon, 4 Feb 2013 15:36:06 +0100 Message-Id: <1359988567-10034-2-git-send-email-michal.simek@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1359988567-10034-1-git-send-email-michal.simek@xilinx.com> References: <1359988567-10034-1-git-send-email-michal.simek@xilinx.com> X-Gm-Message-State: ALoCoQmqaQIO0TolKudxKZR8d/1JuX984UUldN3FmNAWzq0B+KWgUmFz2NaE0gZh0KAw1TVc8ufa Subject: [U-Boot] [PATCH 2/3] arm: zynq: Add SLCR support with system reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/Makefile | 1 + arch/arm/cpu/armv7/zynq/cpu.c | 2 + arch/arm/cpu/armv7/zynq/slcr.c | 63 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynq/hardware.h | 41 ++++++++++++++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 30 +++++++++++++ 5 files changed, 137 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/slcr.c create mode 100644 arch/arm/include/asm/arch-zynq/hardware.h create mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index 499ace4..388085d 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o COBJS-y := timer.o COBJS-y += cpu.o +COBJS-y += slcr.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index ab615cc..91618d3 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -21,11 +21,13 @@ * MA 02111-1307 USA */ #include +#include inline void lowlevel_init(void) {} void reset_cpu(ulong addr) { + zynq_slcr_cpu_reset(); while (1) ; } diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c new file mode 100644 index 0000000..788a8fd --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define SLCR_LOCK_MAGIC 0x767B +#define SLCR_UNLOCK_MAGIC 0xDF0D + +static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ + +void zynq_slcr_lock(void) +{ + if (!slcr_lock) + writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); +} + +void zynq_slcr_unlock(void) +{ + if (slcr_lock) + writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); +} + +/* Reset the entire system */ +void zynq_slcr_cpu_reset(void) +{ + /* + * Unlock the SLCR then reset the system. + * Note that this seems to require raw i/o + * functions or there's a lockup? + */ + zynq_slcr_unlock(); + + /* + * Clear 0x0F000000 bits of reboot status register to workaround + * the FSBL not loading the bitstream after soft-reboot + * This is a temporary solution until we know more. + */ + clrbits_le32(&slcr_base->reboot_status, 0xF000000); + + writel(1, &slcr_base->pss_rst_ctrl); +} diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h new file mode 100644 index 0000000..ad17b27 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define XPSS_SYS_CTRL_BASEADDR 0xF8000000 + +/* Reflect slcr offsets */ +struct slcr_regs { + u32 scl; /* 0x0 */ + u32 slcr_lock; /* 0x4 */ + u32 slcr_unlock; /* 0x8 */ + u32 reserved1[125]; + u32 pss_rst_ctrl; /* 0x200 */ + u32 reserved2[21]; + u32 reboot_status; /* 0x258 */ +}; + +#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR) + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h new file mode 100644 index 0000000..e788900 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +extern void zynq_slcr_lock(void); +extern void zynq_slcr_unlock(void); +extern void zynq_slcr_cpu_reset(void); + +#endif /* _SYS_PROTO_H_ */