Patchwork [U-Boot,V2,1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

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Submitter SRICHARAN R
Date Feb. 4, 2013, 2:29 p.m.
Message ID <1359988164-24840-2-git-send-email-r.sricharan@ti.com>
Download mbox | patch
Permalink /patch/217943/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

SRICHARAN R - Feb. 4, 2013, 2:29 p.m.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
---
 arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
 arch/arm/include/asm/arch-omap5/omap.h |    2 ++
 arch/arm/include/asm/armv7.h           |    1 +
 arch/arm/include/asm/omap_common.h     |    2 ++
 4 files changed, 16 insertions(+), 2 deletions(-)
Tom Rini - Feb. 4, 2013, 3:43 p.m.
On Mon, Feb 04, 2013 at 07:59:20PM +0530, R Sricharan wrote:

> Adding the CPU detection suport for OMAP5430 and
> OMAP5432 ES2.0 SOCs.
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
[snip]
>  /* To be verified */
>  #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
> +#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
>  #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
> +#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
[snip]
> +#define OMAP5430_ES2_0  0x54300200
> +#define OMAP5432_ES2_0  0x54320200

These all have whitespace problems, but git am --whitespace=fix will fix
them.

Reviewed-by: Tom Rini <trini@ti.com>
Nishanth Menon - Feb. 4, 2013, 7:41 p.m.
On 19:59-20130204, R Sricharan wrote:
> Adding the CPU detection suport for OMAP5430 and
> OMAP5432 ES2.0 SOCs.
> 
> Signed-off-by: R Sricharan <r.sricharan@ti.com>
> ---
>  arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
>  arch/arm/include/asm/arch-omap5/omap.h |    2 ++
>  arch/arm/include/asm/armv7.h           |    1 +
>  arch/arm/include/asm/omap_common.h     |    2 ++
>  4 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
> index dfc0e44..0d8c95d 100644
> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
> @@ -216,8 +216,17 @@ void init_omap_revision(void)
>  			break;
>  		}
>  		break;
> -	default:
> -		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> +	case MIDR_CORTEX_A15_R2P2:
> +		switch (readl(CONTROL_ID_CODE)) {
> +		case OMAP5430_CONTROL_ID_CODE_ES2_0:
> +			*omap_si_rev = OMAP5430_ES2_0;
> +			break;
> +		case OMAP5432_CONTROL_ID_CODE_ES2_0:
> +			*omap_si_rev = OMAP5432_ES2_0;
> +			break;
> +		default:
> +			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> +		}

A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse
ID fused in, why would we want to make it a standard to check ARM
revision *and then* cross verify against control fuse verification, *and
then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks
entirely.
>  	}
>  }
>  
> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
> index 873ccd7..71935d8 100644
> --- a/arch/arm/include/asm/arch-omap5/omap.h
> +++ b/arch/arm/include/asm/arch-omap5/omap.h
> @@ -57,7 +57,9 @@
>  
>  /* To be verified */
>  #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
> +#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
>  #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
> +#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
>  
>  /* STD_FUSE_PROD_ID_1 */
>  #define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218)
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index ad9a875..a73630b 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -33,6 +33,7 @@
>  
>  /* Cortex-A15 revisions */
>  #define MIDR_CORTEX_A15_R0P0	0x410FC0F0
> +#define MIDR_CORTEX_A15_R2P2	0x412FC0F2
>  
>  /* CCSIDR */
>  #define CCSIDR_LINE_SIZE_OFFSET		0
> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
> index 2115687..4599167 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -542,4 +542,6 @@ static inline u32 omap_revision(void)
>  #define OMAP5430_SILICON_ID_INVALID	0
>  #define OMAP5430_ES1_0	0x54300100
>  #define OMAP5432_ES1_0	0x54320100
> +#define OMAP5430_ES2_0  0x54300200
> +#define OMAP5432_ES2_0  0x54320200
>  #endif /* _OMAP_COMMON_H_ */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
SRICHARAN R - Feb. 5, 2013, 12:32 p.m.
On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:
> On 19:59-20130204, R Sricharan wrote:
>> Adding the CPU detection suport for OMAP5430 and
>> OMAP5432 ES2.0 SOCs.
>>
>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>> ---
>>   arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
>>   arch/arm/include/asm/arch-omap5/omap.h |    2 ++
>>   arch/arm/include/asm/armv7.h           |    1 +
>>   arch/arm/include/asm/omap_common.h     |    2 ++
>>   4 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
>> index dfc0e44..0d8c95d 100644
>> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
>> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
>> @@ -216,8 +216,17 @@ void init_omap_revision(void)
>>   			break;
>>   		}
>>   		break;
>> -	default:
>> -		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
>> +	case MIDR_CORTEX_A15_R2P2:
>> +		switch (readl(CONTROL_ID_CODE)) {
>> +		case OMAP5430_CONTROL_ID_CODE_ES2_0:
>> +			*omap_si_rev = OMAP5430_ES2_0;
>> +			break;
>> +		case OMAP5432_CONTROL_ID_CODE_ES2_0:
>> +			*omap_si_rev = OMAP5432_ES2_0;
>> +			break;
>> +		default:
>> +			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
>> +		}
>
> A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse
> ID fused in, why would we want to make it a standard to check ARMsilicon
> revision *and then* cross verify against control fuse verification, *and
> then* give up saying we dont support it?
>
> Looks like an over check for me -> IMHO, we should drop the MIDR checks
> entirely.
  In the same context, for some boards in past even in the actual samples
  the CONTROL ID code was reading the older revision. So in those
  cases ARM revision will help to differentiate them.

  But then it should have been in the opposite way, like reading the 
CONTROL_CODE first and then reading the ARM revision if required in 
those cases where is it broken. I will change this logic here.

Regards,
  Sricharan
Nishanth Menon - Feb. 5, 2013, 3:19 p.m.
On 18:02-20130205, R Sricharan wrote:
> On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:
> >On 19:59-20130204, R Sricharan wrote:
> >>Adding the CPU detection suport for OMAP5430 and
> >>OMAP5432 ES2.0 SOCs.
> >>
> >>Signed-off-by: R Sricharan <r.sricharan@ti.com>
> >>---
> >>  arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
> >>  arch/arm/include/asm/arch-omap5/omap.h |    2 ++
> >>  arch/arm/include/asm/armv7.h           |    1 +
> >>  arch/arm/include/asm/omap_common.h     |    2 ++
> >>  4 files changed, 16 insertions(+), 2 deletions(-)
> >>
> >>diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
> >>index dfc0e44..0d8c95d 100644
> >>--- a/arch/arm/cpu/armv7/omap5/hwinit.c
> >>+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
> >>@@ -216,8 +216,17 @@ void init_omap_revision(void)
> >>  			break;
> >>  		}
> >>  		break;
> >>-	default:
> >>-		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> >>+	case MIDR_CORTEX_A15_R2P2:
> >>+		switch (readl(CONTROL_ID_CODE)) {
> >>+		case OMAP5430_CONTROL_ID_CODE_ES2_0:
> >>+			*omap_si_rev = OMAP5430_ES2_0;
> >>+			break;
> >>+		case OMAP5432_CONTROL_ID_CODE_ES2_0:
> >>+			*omap_si_rev = OMAP5432_ES2_0;
> >>+			break;
> >>+		default:
> >>+			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
> >>+		}
> >
> >A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse
> >ID fused in, why would we want to make it a standard to check ARMsilicon
> >revision *and then* cross verify against control fuse verification, *and
> >then* give up saying we dont support it?
> >
> >Looks like an over check for me -> IMHO, we should drop the MIDR checks
> >entirely.
>  In the same context, for some boards in past even in the actual samples
>  the CONTROL ID code was reading the older revision. So in those
>  cases ARM revision will help to differentiate them.
which boards? Almost as a rule the first few samples on almost all
revisions on production floor had messed up control ID, however, beyond
that, all runs are properly updated.
> 
>  But then it should have been in the opposite way, like reading the
> CONTROL_CODE first and then reading the ARM revision if required in
> those cases where is it broken. I will change this logic here.
Having cortex check is just redundant - IMHO, switching it over might be
better, but dropping it is more inline with expectation of the silicon
spec.
SRICHARAN R - Feb. 6, 2013, 6:10 a.m.
Hi,
On Tuesday 05 February 2013 08:49 PM, Nishanth Menon wrote:
> On 18:02-20130205, R Sricharan wrote:
>> On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:
>>> On 19:59-20130204, R Sricharan wrote:
>>>> Adding the CPU detection suport for OMAP5430 and
>>>> OMAP5432 ES2.0 SOCs.
>>>>
>>>> Signed-off-by: R Sricharan <r.sricharan@ti.com>
>>>> ---
>>>>   arch/arm/cpu/armv7/omap5/hwinit.c      |   13 +++++++++++--
>>>>   arch/arm/include/asm/arch-omap5/omap.h |    2 ++
>>>>   arch/arm/include/asm/armv7.h           |    1 +
>>>>   arch/arm/include/asm/omap_common.h     |    2 ++
>>>>   4 files changed, 16 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
>>>> index dfc0e44..0d8c95d 100644
>>>> --- a/arch/arm/cpu/armv7/omap5/hwinit.c
>>>> +++ b/arch/arm/cpu/armv7/omap5/hwinit.c
>>>> @@ -216,8 +216,17 @@ void init_omap_revision(void)
>>>>   			break;
>>>>   		}
>>>>   		break;
>>>> -	default:
>>>> -		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
>>>> +	case MIDR_CORTEX_A15_R2P2:
>>>> +		switch (readl(CONTROL_ID_CODE)) {
>>>> +		case OMAP5430_CONTROL_ID_CODE_ES2_0:
>>>> +			*omap_si_rev = OMAP5430_ES2_0;
>>>> +			break;
>>>> +		case OMAP5432_CONTROL_ID_CODE_ES2_0:
>>>> +			*omap_si_rev = OMAP5432_ES2_0;
>>>> +			break;
>>>> +		default:
>>>> +			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
>>>> +		}
>>>
>>> A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse
>>> ID fused in, why would we want to make it a standard to check ARMsilicon
>>> revision *and then* cross verify against control fuse verification, *and
>>> then* give up saying we dont support it?
>>>
>>> Looks like an over check for me -> IMHO, we should drop the MIDR checks
>>> entirely.
>>   In the same context, for some boards in past even in the actual samples
>>   the CONTROL ID code was reading the older revision. So in those
>>   cases ARM revision will help to differentiate them.
> which boards? Almost as a rule the first few samples on almost all
> revisions on production floor had messed up control ID, however, beyond
> that, all runs are properly updated.
>>
  I have seen this issue on some OMAP4 revisions as well. It was only 
after that we introduced this logic of double checking using ARM 
revision ID.
>>   But then it should have been in the opposite way, like reading the
>> CONTROL_CODE first and then reading the ARM revision if required in
>> those cases where is it broken. I will change this logic here.
> Having cortex check is just redundant - IMHO, switching it over might be
> better, but dropping it is more inline with expectation of the silicon
> spec.
>
  According to me the best way to do it is, use CONTROL_ID first and
  then use ARM revision for those which has wrong IDs. This will always
  be a fool proof even for those non-working boards.

Regards,
  Sricharan

Patch

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index dfc0e44..0d8c95d 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -216,8 +216,17 @@  void init_omap_revision(void)
 			break;
 		}
 		break;
-	default:
-		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+	case MIDR_CORTEX_A15_R2P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP5430_CONTROL_ID_CODE_ES2_0:
+			*omap_si_rev = OMAP5430_ES2_0;
+			break;
+		case OMAP5432_CONTROL_ID_CODE_ES2_0:
+			*omap_si_rev = OMAP5432_ES2_0;
+			break;
+		default:
+			*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+		}
 	}
 }
 
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 873ccd7..71935d8 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -57,7 +57,9 @@ 
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 
 /* STD_FUSE_PROD_ID_1 */
 #define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index ad9a875..a73630b 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -33,6 +33,7 @@ 
 
 /* Cortex-A15 revisions */
 #define MIDR_CORTEX_A15_R0P0	0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2	0x412FC0F2
 
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2115687..4599167 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -542,4 +542,6 @@  static inline u32 omap_revision(void)
 #define OMAP5430_SILICON_ID_INVALID	0
 #define OMAP5430_ES1_0	0x54300100
 #define OMAP5432_ES1_0	0x54320100
+#define OMAP5430_ES2_0  0x54300200
+#define OMAP5432_ES2_0  0x54320200
 #endif /* _OMAP_COMMON_H_ */