diff mbox

[U-Boot,v2,10/10] MIPS: start.S: emulate REVISION register for qemu-malta

Message ID 1359821166-32352-11-git-send-email-juhosg@openwrt.org
State Superseded
Delegated to: Daniel Schwierzeck
Headers show

Commit Message

Gabor Juhos Feb. 2, 2013, 4:06 p.m. UTC 
On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.

This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
Changes since v1:
 - rebased against mips/testing

Changes since RFC: ---
---
 arch/mips/cpu/mips32/start.S |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 7373d4e..6f6e92b 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -57,7 +57,7 @@  _start:
 	 nop
 
 	.org 0x10
-#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
 	/*
 	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
 	 * access external NOR flashes. If the board boots from NOR flash the
@@ -67,6 +67,12 @@  _start:
 	 */
 	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
 	.word 0x0
+#elif defined(CONFIG_QEMU_MALTA)
+	/*
+	 * Linux expects the Board ID here.
+	 */
+	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
+	.word 0x00000000
 #endif
 
 	.org 0x200