Patchwork [ARM,2/2] Load-acquire, store-release atomics in AArch32 ARMv8

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Submitter Kyrylo Tkachov
Date Feb. 1, 2013, 5:38 p.m.
Message ID <003201ce00a2$f4e9d470$debd7d50$@tkachov@arm.com>
Download mbox | patch
Permalink /patch/217544/
State New
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Comments

Kyrylo Tkachov - Feb. 1, 2013, 5:38 p.m.
Ummm... forgot the patch, sorry!

> -----Original Message-----
> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> owner@gcc.gnu.org] On Behalf Of Kyrylo Tkachov
> Sent: 01 February 2013 17:37
> To: gcc-patches@gcc.gnu.org
> Cc: Ramana Radhakrishnan; Richard Earnshaw; Marcus Shawcroft
> Subject: [PATCH][ARM][2/2] Load-acquire, store-release atomics in
> AArch32 ARMv8
> 
> Hi all,
> This patch adds the tests for the ARMv8 AArch32 implementation of
> atomics.
> It refactors some aarch64 tests and reuses them.
> 
> Ok for trunk or for the next stage 1 (together with part 1 at
> http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01441.html)?
> 
> Thanks,
> Kyrill
> 
> 
> gcc/testsuite/ChangeLog
> 
> 2013-01-25  Kyrylo Tkachov  <kyrylo.tkachov at arm.com>
> 
> 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move
> test
> body
> 	from here...
> 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to
> here.
> 	* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-acquire.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-char.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-char.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-consume.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-consume.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
> 	* gcc.target/aarch64/atomic-op-int.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-release.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-release.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
> 	* gcc.target/aarch64/atomic-op-short.c: Move test body from
> here...
> 	* gcc.target/aarch64/atomic-op-short.x: ... to here.
> 	* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
> 	* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
> 	* gcc.target/arm/atomic-op-acquire.c: Likewise.
> 	* gcc.target/arm/atomic-op-char.c: Likewise.
> 	* gcc.target/arm/atomic-op-consume.c: Likewise.
> 	* gcc.target/arm/atomic-op-int.c: Likewise.
> 	* gcc.target/arm/atomic-op-relaxed.c: Likewise.
> 	* gcc.target/arm/atomic-op-release.c: Likewise.
> 	* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
> 	* gcc.target/arm/atomic-op-short.c: Likewise.
> 
> 
>
Kyrylo Tkachov - March 22, 2013, 12:09 p.m.
Ping?

http://gcc.gnu.org/ml/gcc-patches/2013-02/msg00023.html

I thought this was ok'd for 4.9 but I can't seem to find the ok email in the
archives

Thanks,
Kyrill

> -----Original Message-----
> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> owner@gcc.gnu.org] On Behalf Of Kyrylo Tkachov
> Sent: 01 February 2013 17:39
> To: gcc-patches@gcc.gnu.org
> Cc: Ramana Radhakrishnan; Richard Earnshaw; Marcus Shawcroft
> Subject: RE: [PATCH][ARM][2/2] Load-acquire, store-release atomics in
> AArch32 ARMv8
> 
> Ummm... forgot the patch, sorry!
> 
> > -----Original Message-----
> > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> > owner@gcc.gnu.org] On Behalf Of Kyrylo Tkachov
> > Sent: 01 February 2013 17:37
> > To: gcc-patches@gcc.gnu.org
> > Cc: Ramana Radhakrishnan; Richard Earnshaw; Marcus Shawcroft
> > Subject: [PATCH][ARM][2/2] Load-acquire, store-release atomics in
> > AArch32 ARMv8
> >
> > Hi all,
> > This patch adds the tests for the ARMv8 AArch32 implementation of
> > atomics.
> > It refactors some aarch64 tests and reuses them.
> >
> > Ok for trunk or for the next stage 1 (together with part 1 at
> > http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01441.html)?
> >
> > Thanks,
> > Kyrill
> >
> >
> > gcc/testsuite/ChangeLog
> >
> > 2013-01-25  Kyrylo Tkachov  <kyrylo.tkachov at arm.com>
> >
> > 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move
> > test
> > body
> > 	from here...
> > 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to
> > here.
> > 	* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-acquire.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-char.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-char.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-consume.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-consume.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
> > 	* gcc.target/aarch64/atomic-op-int.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-release.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-release.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
> > 	* gcc.target/aarch64/atomic-op-short.c: Move test body from
> > here...
> > 	* gcc.target/aarch64/atomic-op-short.x: ... to here.
> > 	* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
> > 	* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
> > 	* gcc.target/arm/atomic-op-acquire.c: Likewise.
> > 	* gcc.target/arm/atomic-op-char.c: Likewise.
> > 	* gcc.target/arm/atomic-op-consume.c: Likewise.
> > 	* gcc.target/arm/atomic-op-int.c: Likewise.
> > 	* gcc.target/arm/atomic-op-relaxed.c: Likewise.
> > 	* gcc.target/arm/atomic-op-release.c: Likewise.
> > 	* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
> > 	* gcc.target/arm/atomic-op-short.c: Likewise.
> >
> >
> >
Richard Earnshaw - March 22, 2013, 3:51 p.m.
On 01/02/13 17:38, Kyrylo Tkachov wrote:
> Ummm... forgot the patch, sorry!
>
>> -----Original Message-----
>> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
>> owner@gcc.gnu.org] On Behalf Of Kyrylo Tkachov
>> Sent: 01 February 2013 17:37
>> To: gcc-patches@gcc.gnu.org
>> Cc: Ramana Radhakrishnan; Richard Earnshaw; Marcus Shawcroft
>> Subject: [PATCH][ARM][2/2] Load-acquire, store-release atomics in
>> AArch32 ARMv8
>>
>> Hi all,
>> This patch adds the tests for the ARMv8 AArch32 implementation of
>> atomics.
>> It refactors some aarch64 tests and reuses them.
>>
>> Ok for trunk or for the next stage 1 (together with part 1 at
>> http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01441.html)?
>>
>> Thanks,
>> Kyrill
>>
>>
>> gcc/testsuite/ChangeLog
>>
>> 2013-01-25  Kyrylo Tkachov  <kyrylo.tkachov at arm.com>
>>
>> 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move
>> test
>> body
>> 	from here...
>> 	* gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to
>> here.
>> 	* gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-acq_rel.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-acquire.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-acquire.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-char.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-char.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-consume.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-consume.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-int.c: Move test body from here...
>> 	* gcc.target/aarch64/atomic-op-int.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-relaxed.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-relaxed.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-release.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-release.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-seq_cst.x: ... to here.
>> 	* gcc.target/aarch64/atomic-op-short.c: Move test body from
>> here...
>> 	* gcc.target/aarch64/atomic-op-short.x: ... to here.
>> 	* gcc.target/arm/atomic-comp-swap-release-acquire.c: New test.
>> 	* gcc.target/arm/atomic-op-acq_rel.c: Likewise.
>> 	* gcc.target/arm/atomic-op-acquire.c: Likewise.
>> 	* gcc.target/arm/atomic-op-char.c: Likewise.
>> 	* gcc.target/arm/atomic-op-consume.c: Likewise.
>> 	* gcc.target/arm/atomic-op-int.c: Likewise.
>> 	* gcc.target/arm/atomic-op-relaxed.c: Likewise.
>> 	* gcc.target/arm/atomic-op-release.c: Likewise.
>> 	* gcc.target/arm/atomic-op-seq_cst.c: Likewise.
>> 	* gcc.target/arm/atomic-op-short.c: Likewise.
>>
>>
>>


OK.

R.

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
index 1492e25..9785bca 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
@@ -1,41 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-#define STRONG 0
-#define WEAK 1
-int v = 0;
-
-int
-atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
-{
-  return __atomic_compare_exchange (&v, &a, &b,
-				    STRONG, __ATOMIC_RELEASE,
-				    __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
-{
-  return __atomic_compare_exchange (&v, &a, &b,
-				    WEAK, __ATOMIC_RELEASE,
-				    __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
-{
-  return __atomic_compare_exchange_n (&v, &a, b,
-				      STRONG, __ATOMIC_RELEASE,
-				      __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
-{
-  return __atomic_compare_exchange_n (&v, &a, b,
-				      WEAK, __ATOMIC_RELEASE,
-				      __ATOMIC_ACQUIRE);
-}
+#include "atomic-comp-swap-release-acquire.x"
 
 /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
 /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
new file mode 100644
index 0000000..4403afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
@@ -0,0 +1,36 @@ 
+
+#define STRONG 0
+#define WEAK 1
+int v = 0;
+
+int
+atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange (&v, &a, &b,
+				    STRONG, __ATOMIC_RELEASE,
+				    __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange (&v, &a, &b,
+				    WEAK, __ATOMIC_RELEASE,
+				    __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange_n (&v, &a, b,
+				      STRONG, __ATOMIC_RELEASE,
+				      __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange_n (&v, &a, b,
+				      WEAK, __ATOMIC_RELEASE,
+				      __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
index be6682f..8569ac0 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_ACQ_REL (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
-}
-
-int
-atomic_fetch_sub_ACQ_REL (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
-}
-
-int
-atomic_fetch_and_ACQ_REL (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
-}
-
-int
-atomic_fetch_nand_ACQ_REL (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
-}
-
-int
-atomic_fetch_xor_ACQ_REL (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
-}
-
-int
-atomic_fetch_or_ACQ_REL (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
-}
+#include "atomic-op-acq_rel.x"
 
 /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
new file mode 100644
index 0000000..9970bbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_ACQ_REL (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_sub_ACQ_REL (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_and_ACQ_REL (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_nand_ACQ_REL (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_xor_ACQ_REL (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_or_ACQ_REL (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
index 023797e..57e6d57 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_ACQUIRE (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_fetch_sub_ACQUIRE (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_fetch_and_ACQUIRE (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_fetch_nand_ACQUIRE (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_fetch_xor_ACQUIRE (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
-}
-
-int
-atomic_fetch_or_ACQUIRE (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
-}
+#include "atomic-op-acquire.x"
 
 /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
new file mode 100644
index 0000000..7eeb7f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_ACQUIRE (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_sub_ACQUIRE (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_and_ACQUIRE (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_nand_ACQUIRE (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_xor_ACQUIRE (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_or_ACQUIRE (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
index 8dcc4c8..d6c2aa5 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-char v = 0;
-
-char
-atomic_fetch_add_RELAXED (char a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
-}
-
-char
-atomic_fetch_sub_RELAXED (char a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
-}
-
-char
-atomic_fetch_and_RELAXED (char a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
-}
-
-char
-atomic_fetch_nand_RELAXED (char a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
-}
-
-char
-atomic_fetch_xor_RELAXED (char a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
-}
-
-char
-atomic_fetch_or_RELAXED (char a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
-}
+#include "atomic-op-char.x"
 
 /* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
new file mode 100644
index 0000000..a543aa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
@@ -0,0 +1,37 @@ 
+char v = 0;
+
+char
+atomic_fetch_add_RELAXED (char a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_sub_RELAXED (char a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_and_RELAXED (char a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_nand_RELAXED (char a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_xor_RELAXED (char a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_or_RELAXED (char a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
index e3afde2..38d6c2c 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_CONSUME (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
-}
-
-int
-atomic_fetch_sub_CONSUME (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
-}
-
-int
-atomic_fetch_and_CONSUME (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
-}
-
-int
-atomic_fetch_nand_CONSUME (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
-}
-
-int
-atomic_fetch_xor_CONSUME (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
-}
-
-int
-atomic_fetch_or_CONSUME (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
-}
+#include "atomic-op-consume.x"
 
 /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
new file mode 100644
index 0000000..c6b0792
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_CONSUME (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_sub_CONSUME (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_and_CONSUME (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_nand_CONSUME (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_xor_CONSUME (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_or_CONSUME (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
index 065ccf5..9ad7a79 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_RELAXED (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_sub_RELAXED (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_and_RELAXED (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_nand_RELAXED (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_xor_RELAXED (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_or_RELAXED (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
-}
+#include "atomic-op-int.x"
 
 /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
new file mode 100644
index 0000000..74ab632
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
index 065ccf5..cd3fe2c 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_RELAXED (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_sub_RELAXED (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_and_RELAXED (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_nand_RELAXED (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_xor_RELAXED (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
-}
-
-int
-atomic_fetch_or_RELAXED (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
-}
+#include "atomic-op-relaxed.x"
 
 /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
new file mode 100644
index 0000000..74ab632
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
index 3d8c49c..2fc04b2 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_RELEASE (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
-}
-
-int
-atomic_fetch_sub_RELEASE (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
-}
-
-int
-atomic_fetch_and_RELEASE (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
-}
-
-int
-atomic_fetch_nand_RELEASE (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
-}
-
-int
-atomic_fetch_xor_RELEASE (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
-}
-
-int
-atomic_fetch_or_RELEASE (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
-}
+#include "atomic-op-release.x"
 
 /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
new file mode 100644
index 0000000..343f09b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_RELEASE (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_sub_RELEASE (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_and_RELEASE (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_nand_RELEASE (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_xor_RELEASE (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_or_RELEASE (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
index a8ad4f8..202d471 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-int v = 0;
-
-int
-atomic_fetch_add_SEQ_CST (int a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
-}
-
-int
-atomic_fetch_sub_SEQ_CST (int a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
-}
-
-int
-atomic_fetch_and_SEQ_CST (int a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
-}
-
-int
-atomic_fetch_nand_SEQ_CST (int a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
-}
-
-int
-atomic_fetch_xor_SEQ_CST (int a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
-}
-
-int
-atomic_fetch_or_SEQ_CST (int a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
-}
+#include "atomic-op-seq_cst.x"
 
 /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
new file mode 100644
index 0000000..e654a74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
@@ -0,0 +1,37 @@ 
+int v = 0;
+
+int
+atomic_fetch_add_SEQ_CST (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_sub_SEQ_CST (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_and_SEQ_CST (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_nand_SEQ_CST (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_xor_SEQ_CST (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_or_SEQ_CST (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
index 30db340..39e71c1 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
@@ -1,43 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 
-short v = 0;
-
-short
-atomic_fetch_add_RELAXED (short a)
-{
-  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
-}
-
-short
-atomic_fetch_sub_RELAXED (short a)
-{
-  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
-}
-
-short
-atomic_fetch_and_RELAXED (short a)
-{
-  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
-}
-
-short
-atomic_fetch_nand_RELAXED (short a)
-{
-  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
-}
-
-short
-atomic_fetch_xor_RELAXED (short a)
-{
-  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
-}
-
-short
-atomic_fetch_or_RELAXED (short a)
-{
-  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
-}
+#include "atomic-op-short.x"
 
 /* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
 /* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
new file mode 100644
index 0000000..2fd70f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
@@ -0,0 +1,37 @@ 
+short v = 0;
+
+short
+atomic_fetch_add_RELAXED (short a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_sub_RELAXED (short a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_and_RELAXED (short a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_nand_RELAXED (short a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_xor_RELAXED (short a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_or_RELAXED (short a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
new file mode 100644
index 0000000..1c1028c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-comp-swap-release-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "stlex" 4 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
new file mode 100644
index 0000000..2f091f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-acq_rel.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
new file mode 100644
index 0000000..977c2fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc/testsuite/gcc.target/arm/atomic-op-char.c
new file mode 100644
index 0000000..63e34c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-char.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-char.x"
+
+/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
new file mode 100644
index 0000000..8e1779e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-consume.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc/testsuite/gcc.target/arm/atomic-op-int.c
new file mode 100644
index 0000000..1476c52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-int.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-int.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
new file mode 100644
index 0000000..cae8323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-relaxed.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc/testsuite/gcc.target/arm/atomic-op-release.c
new file mode 100644
index 0000000..415f463
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-release.c
@@ -0,0 +1,11 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-release.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
new file mode 100644
index 0000000..c7b93eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
@@ -0,0 +1,10 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-seq_cst.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc/testsuite/gcc.target/arm/atomic-op-short.c
new file mode 100644
index 0000000..7e5a603
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-short.c
@@ -0,0 +1,11 @@ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-short.x"
+
+/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+