From patchwork Thu Jan 31 22:10:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [3.5.y.z, extended, stable] Patch "drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for" has been added to staging queue Date: Thu, 31 Jan 2013 12:10:31 -0000 From: Herton Ronaldo Krzesinski X-Patchwork-Id: 217273 Message-Id: <1359670231-17010-1-git-send-email-herton.krzesinski@canonical.com> To: Chris Wilson Cc: Daniel Vetter , Ben Widawsky , kernel-team@lists.ubuntu.com This is a note to let you know that I have just added a patch titled drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for to the linux-3.5.y-queue branch of the 3.5.y.z extended stable tree which can be found at: http://kernel.ubuntu.com/git?p=ubuntu/linux.git;a=shortlog;h=refs/heads/linux-3.5.y-queue If you, or anyone else, feels it should not be added to this tree, please reply to this email. For more information about the 3.5.y.z tree, see https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable Thanks. -Herton ------ >From ca580ba69e5f2a6e5d4c57e4c95c2bc06cd57db4 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 20 Jan 2013 16:33:32 +0000 Subject: [PATCH] drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits commit f05bb0c7b624252a5e768287e340e8e45df96e42 upstream. On SNB, if bit 13 of GFX_MODE, Flush TLB Invalidate Mode, is not set to 1, the hardware can not program the scanline values. Those scanline values then control when the signal is sent from the display engine to the render ring for MI_WAIT_FOR_EVENTs. Note setting this bit means that TLB invalidations must be performed explicitly through the appropriate bits being set in PIPE_CONTROL. References: https://bugzilla.kernel.org/show_bug.cgi?id=52311 Signed-off-by: Chris Wilson Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter Signed-off-by: Herton Ronaldo Krzesinski --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 1 file changed, 5 insertions(+) -- 1.7.9.5 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 78486c7..e75d794 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -421,6 +421,11 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (INTEL_INFO(dev)->gen >= 6) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); + /* Required for the hardware to program scanline values for waiting */ + if (INTEL_INFO(dev)->gen == 6) + I915_WRITE(GFX_MODE, + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); + if (IS_GEN7(dev)) I915_WRITE(GFX_MODE_GEN7, _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |