From patchwork Thu Jan 31 05:52:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 217093 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4BD8F2C0294 for ; Thu, 31 Jan 2013 16:53:24 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B5C694A144; Thu, 31 Jan 2013 06:53:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V75r1o4F4ZVz; Thu, 31 Jan 2013 06:53:09 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 40A424A188; Thu, 31 Jan 2013 06:52:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD9484A155 for ; Thu, 31 Jan 2013 06:52:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aNHCEB6GqV3P for ; Thu, 31 Jan 2013 06:52:17 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 5A4B44A133 for ; Thu, 31 Jan 2013 06:52:12 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0V5q8nZ023346 for ; Wed, 30 Jan 2013 23:52:09 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0V5q77D027919 for ; Thu, 31 Jan 2013 11:22:08 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Thu, 31 Jan 2013 11:22:07 +0530 Received: from localhost.localdomain (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0V5q5Pt024468; Thu, 31 Jan 2013 11:22:07 +0530 From: R Sricharan To: Date: Thu, 31 Jan 2013 11:22:04 +0530 Message-ID: <1359611525-19017-7-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359611525-19017-1-git-send-email-r.sricharan@ti.com> References: <1359611525-19017-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH 6/7] ARM: OMAP4+: Make control module register structure generic X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Lokesh Vutla A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 5 +- arch/arm/cpu/armv7/omap4/hw_data.c | 4 + arch/arm/cpu/armv7/omap4/hwinit.c | 36 ++++----- arch/arm/cpu/armv7/omap4/prcm-regs.c | 20 +++++ arch/arm/cpu/armv7/omap5/hw_data.c | 4 +- arch/arm/cpu/armv7/omap5/hwinit.c | 102 +++++++++++------------- arch/arm/cpu/armv7/omap5/prcm-regs.c | 74 +++++++++++++++++ arch/arm/include/asm/arch-omap4/omap.h | 31 +------ arch/arm/include/asm/arch-omap5/omap.h | 84 +------------------ arch/arm/include/asm/omap_common.h | 91 +++++++++++++++++++++ drivers/mmc/omap_hsmmc.c | 25 +++--- 11 files changed, 269 insertions(+), 207 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index c93794d..277dc66 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -244,10 +244,7 @@ int checkboard(void) */ u32 get_device_type(void) { - struct omap_sys_ctrl_regs *ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - - return (readl(&ctrl->control_status) & + return (readl((*ctrl)->control_status) & (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 17c1453..de449e4 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -37,6 +37,8 @@ struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; /* * The M & N values in the following tables are created using the @@ -454,4 +456,6 @@ void hw_data_init(void) printf("\n INVALID OMAP REVISION "); } + *ctrl = &omap4_ctrl; + prcm_init(omap_vcores); } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index f4123aa..2db517b 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; void do_io_settings(void) { u32 lpddr2io; - struct control_lpddr2io_regs *lpddr2io_regs = - (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -72,20 +68,20 @@ void do_io_settings(void) lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; /* EMIF1 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); + (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); /* EMIF2 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); + (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); /* * Some of these settings (TRIM values) come from eFuse and are @@ -93,16 +89,16 @@ void do_io_settings(void) * calibration of the device. Do the software over-ride only if * the device is not correctly trimmed */ - if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_iva_voltage_ctrl); + (*ctrl)->control_ldosram_iva_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_mpu_voltage_ctrl); + (*ctrl)->control_ldosram_mpu_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_core_voltage_ctrl); + (*ctrl)->control_ldosram_core_voltage_ctrl); } /* @@ -110,11 +106,11 @@ void do_io_settings(void) * i. unconditionally for all 4430 * ii. only if un-trimmed for 4460 */ - if (!readl(&ctrl->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); - if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); + if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index d19e5b4..8f63283 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -265,3 +265,23 @@ struct prcm_regs const omap4_prcm = { .prm_vc_cfg_i2c_mode = 0x4a307ba8, .prm_vc_cfg_i2c_clk = 0x4a307bac, }; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_id_code = 0x4A002204, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, +}; diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index f843159..e1388bb 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -37,6 +37,8 @@ struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -422,6 +424,6 @@ void hw_data_init(void) default: printf("\n INVALID OMAP REVISION "); } - + *ctrl = &omap5_ctrl; prcm_init(omap_vcores); } diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 4def422..1863c69 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -56,76 +56,71 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); + (*ctrl)->control_ddrch1_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); + (*ctrl)->control_ddrch1_1); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); + (*ctrl)->control_ddrch2_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); + (*ctrl)->control_ddrch2_1); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); + (*ctrl)->control_lpddr2ch1_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); + (*ctrl)->control_lpddr2ch1_1); writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); + (*ctrl)->control_ddrio_0); writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); + (*ctrl)->control_ddrio_1); writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + (*ctrl)->control_ddrio_2); } /* DDR3 specific IO settings */ static void io_settings_ddr3(void) { u32 io_settings = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch1_0)); + (*ctrl)->control_ddr3ch1_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_0)); + (*ctrl)->control_ddrch1_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_1)); + (*ctrl)->control_ddrch1_1); writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch2_0)); + (*ctrl)->control_ddr3ch2_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_0)); + (*ctrl)->control_ddrch2_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_1)); + (*ctrl)->control_ddrch2_1); writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_0)); + (*ctrl)->control_ddrio_0); writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_1)); + (*ctrl)->control_ddrio_1); writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_2)); + (*ctrl)->control_ddrio_2); /* omap5432 does not use lpddr2 */ - writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); - writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + writel(0x0, (*ctrl)->control_lpddr2ch1_0); + writel(0x0, (*ctrl)->control_lpddr2ch1_1); writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); + (*ctrl)->control_emif1_sdram_config_ext); writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + (*ctrl)->control_emif2_sdram_config_ext); /* Disable DLL select */ - io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif1_sdram_config)); + (*ctrl)->control_port_emif1_sdram_config); - io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif2_sdram_config)); + (*ctrl)->control_port_emif2_sdram_config); } /* @@ -134,62 +129,60 @@ static void io_settings_ddr3(void) void do_io_settings(void) { u32 io_settings = 0, mask = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; /* Impedance settings EMMC, C2C 1,2, hsi2 */ mask = (ds_mask << 2) | (ds_mask << 8) | (ds_mask << 16) | (ds_mask << 18); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_0) & (~mask); io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | (ds_45_ohm << 18) | (ds_60_ohm << 2); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_0); /* Impedance settings Mcspi2 */ mask = (ds_mask << 30); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 30); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_1); /* Impedance settings C2C 3,4 */ mask = (ds_mask << 14) | (ds_mask << 16); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_2) & (~mask); io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_2); /* Slew rate settings EMMC, C2C 1,2 */ mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_0) & (~mask); io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_0); /* Slew rate settings hsi2, Mcspi2 */ mask = (sc_mask << 24) | (sc_mask << 28); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_1) & (~mask); io_settings |= (sc_fast << 28) | (sc_fast << 24); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_1); /* Slew rate settings C2C 3,4 */ mask = (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_2) & (~mask); io_settings |= (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_2); /* impedance and slew rate settings for usb */ mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); - io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart3io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | (ds_60_ohm << 23) | (sc_fast << 20) | (sc_fast << 17) | (sc_fast << 14); - writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart3io_padconf_1); if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); @@ -197,25 +190,22 @@ void do_io_settings(void) io_settings_ddr3(); /* Efuse settings */ - writel(EFUSE_1, &(ioregs_base->control_efuse_1)); - writel(EFUSE_2, &(ioregs_base->control_efuse_2)); - writel(EFUSE_3, &(ioregs_base->control_efuse_3)); - writel(EFUSE_4, &(ioregs_base->control_efuse_4)); + writel(EFUSE_1, (*ctrl)->control_efuse_1); + writel(EFUSE_2, (*ctrl)->control_efuse_2); + writel(EFUSE_3, (*ctrl)->control_efuse_3); + writel(EFUSE_4, (*ctrl)->control_efuse_4); } #endif void config_data_eye_leveling_samples(u32 emif_base) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index c12f862..07e7ade 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -276,3 +276,77 @@ struct prcm_regs const omap5_es1_prcm = { .prm_sldo_mm_setup = 0x4ae07bd4, .prm_sldo_mm_ctrl = 0x4ae07bd8, }; + +struct omap_sys_ctrl_regs const omap5_ctrl = { + .control_status = 0x4A002134, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, + .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, + .control_padconf_mode = 0x4AE0CDA8, + .control_xtal_oscillator = 0x4AE0CDAC, + .control_i2c_2 = 0x4AE0CDB0, + .control_ckobuffer = 0x4AE0CDB4, + .control_wkup_control_spare_rw = 0x4AE0CDB8, + .control_wkup_control_spare_r = 0x4AE0CDBC, + .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, + .control_srcomp_east_side_wkup = 0x4AE0CDC4, + .control_efuse_1 = 0x4AE0CDC8, + .control_efuse_2 = 0x4AE0CDCC, + .control_efuse_3 = 0x4AE0CDD0, + .control_efuse_4 = 0x4AE0CDD4, + .control_efuse_5 = 0x4AE0CDD8, + .control_efuse_6 = 0x4AE0CDDC, + .control_efuse_7 = 0x4AE0CDE0, + .control_efuse_8 = 0x4AE0CDE4, + .control_efuse_9 = 0x4AE0CDE8, + .control_efuse_10 = 0x4AE0CDEC, + .control_efuse_11 = 0x4AE0CDF0, + .control_efuse_12 = 0x4AE0CDF4, + .control_efuse_13 = 0x4AE0CDF8, +}; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 1c0ce9b..ea7471a 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -132,34 +132,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - unsigned int pad1[129]; - unsigned int control_id_code; /* 0x4A002204 */ - unsigned int pad11[22]; - unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ - unsigned int pad2[24]; /* 0x4a002264 */ - unsigned int control_status; /* 0x4a0022c4 */ - unsigned int pad3[22]; /* 0x4a0022c8 */ - unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ - unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ - unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ - unsigned int pad4[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ - unsigned int pad5[63]; - unsigned int control_efuse_1; /* 0x4A100700 */ - unsigned int control_efuse_2; /* 0x4A100704 */ -}; - -struct control_lpddr2io_regs { - unsigned int control_lpddr2io1_0; - unsigned int control_lpddr2io1_1; - unsigned int control_lpddr2io1_2; - unsigned int control_lpddr2io1_3; - unsigned int control_lpddr2io2_0; - unsigned int control_lpddr2io2_1; - unsigned int control_lpddr2io2_2; - unsigned int control_lpddr2io2_3; -}; #endif /* __ASSEMBLY__ */ /* @@ -180,7 +152,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 7123694..3ec8a9a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -131,87 +131,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - u32 pad0[77]; /* 0x4A002000 */ - u32 control_status; /* 0x4A002134 */ - u32 pad1[794]; /* 0x4A002138 */ - u32 control_paconf_global; /* 0x4A002DA0 */ - u32 control_paconf_mode; /* 0x4A002DA4 */ - u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ - u32 control_smart1io_padconf_1; /* 0x4A002DAC */ - u32 control_smart1io_padconf_2; /* 0x4A002DB0 */ - u32 control_smart2io_padconf_0; /* 0x4A002DB4 */ - u32 control_smart2io_padconf_1; /* 0x4A002DB8 */ - u32 control_smart2io_padconf_2; /* 0x4A002DBC */ - u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ - u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ - u32 pad2[14]; - u32 control_pbias; /* 0x4A002E00 */ - u32 control_i2c_0; /* 0x4A002E04 */ - u32 control_camera_rx; /* 0x4A002E08 */ - u32 control_hdmi_tx_phy; /* 0x4A002E0C */ - u32 control_uniportm; /* 0x4A002E10 */ - u32 control_dsiphy; /* 0x4A002E14 */ - u32 control_mcbsplp; /* 0x4A002E18 */ - u32 control_usb2phycore; /* 0x4A002E1C */ - u32 control_hdmi_1; /*0x4A002E20*/ - u32 control_hsi; /*0x4A002E24*/ - u32 pad3[2]; - u32 control_ddr3ch1_0; /*0x4A002E30*/ - u32 control_ddr3ch2_0; /*0x4A002E34*/ - u32 control_ddrch1_0; /*0x4A002E38*/ - u32 control_ddrch1_1; /*0x4A002E3C*/ - u32 control_ddrch2_0; /*0x4A002E40*/ - u32 control_ddrch2_1; /*0x4A002E44*/ - u32 control_lpddr2ch1_0; /*0x4A002E48*/ - u32 control_lpddr2ch1_1; /*0x4A002E4C*/ - u32 control_ddrio_0; /*0x4A002E50*/ - u32 control_ddrio_1; /*0x4A002E54*/ - u32 control_ddrio_2; /*0x4A002E58*/ - u32 control_hyst_1; /*0x4A002E5C*/ - u32 control_usbb_hsic_control; /*0x4A002E60*/ - u32 control_c2c; /*0x4A002E64*/ - u32 control_core_control_spare_rw; /*0x4A002E68*/ - u32 control_core_control_spare_r; /*0x4A002E6C*/ - u32 control_core_control_spare_r_c0; /*0x4A002E70*/ - u32 control_srcomp_north_side; /*0x4A002E74*/ - u32 control_srcomp_south_side; /*0x4A002E78*/ - u32 control_srcomp_east_side; /*0x4A002E7C*/ - u32 control_srcomp_west_side; /*0x4A002E80*/ - u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3679394]; - u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ - u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ - u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ - u32 pad5[10]; - u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ - u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ - u32 pad6[789]; - u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ - u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ - u32 control_padconf_mode; /* 0x4AE0CDA8 */ - u32 control_xtal_oscillator; /* 0x4AE0CDAC */ - u32 control_i2c_2; /* 0x4AE0CDB0 */ - u32 control_ckobuffer; /* 0x4AE0CDB4 */ - u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */ - u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */ - u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */ - u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */ - u32 control_efuse_1; /* 0x4AE0CDC8 */ - u32 control_efuse_2; /* 0x4AE0CDCC */ - u32 control_efuse_3; /* 0x4AE0CDD0 */ - u32 control_efuse_4; /* 0x4AE0CDD4 */ - u32 control_efuse_5; /* 0x4AE0CDD8 */ - u32 control_efuse_6; /* 0x4AE0CDDC */ - u32 control_efuse_7; /* 0x4AE0CDE0 */ - u32 control_efuse_8; /* 0x4AE0CDE4 */ - u32 control_efuse_9; /* 0x4AE0CDE8 */ - u32 control_efuse_10; /* 0x4AE0CDEC */ - u32 control_efuse_11; /* 0x4AE0CDF0 */ - u32 control_efuse_12; /* 0x4AE0CDF4 */ - u32 control_efuse_13; /* 0x4AE0CDF8 */ -}; - /* Output impedance control */ #define ds_120_ohm 0x0 #define ds_60_ohm 0x1 @@ -273,7 +192,8 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index a45ede4..ef1621f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -326,6 +326,94 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct omap_sys_ctrl_regs { + u32 control_status; + u32 control_id_code; + u32 control_std_fuse_opp_bgap; + u32 control_ldosram_iva_voltage_ctrl; + u32 control_ldosram_mpu_voltage_ctrl; + u32 control_ldosram_core_voltage_ctrl; + u32 control_paconf_global; + u32 control_paconf_mode; + u32 control_smart1io_padconf_0; + u32 control_smart1io_padconf_1; + u32 control_smart1io_padconf_2; + u32 control_smart2io_padconf_0; + u32 control_smart2io_padconf_1; + u32 control_smart2io_padconf_2; + u32 control_smart3io_padconf_0; + u32 control_smart3io_padconf_1; + u32 control_pbias; + u32 control_i2c_0; + u32 control_camera_rx; + u32 control_hdmi_tx_phy; + u32 control_uniportm; + u32 control_dsiphy; + u32 control_mcbsplp; + u32 control_usb2phycore; + u32 control_hdmi_1; + u32 control_hsi; + u32 control_ddr3ch1_0; + u32 control_ddr3ch2_0; + u32 control_ddrch1_0; + u32 control_ddrch1_1; + u32 control_ddrch2_0; + u32 control_ddrch2_1; + u32 control_lpddr2ch1_0; + u32 control_lpddr2ch1_1; + u32 control_ddrio_0; + u32 control_ddrio_1; + u32 control_ddrio_2; + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; + u32 control_hyst_1; + u32 control_usbb_hsic_control; + u32 control_c2c; + u32 control_core_control_spare_rw; + u32 control_core_control_spare_r; + u32 control_core_control_spare_r_c0; + u32 control_srcomp_north_side; + u32 control_srcomp_south_side; + u32 control_srcomp_east_side; + u32 control_srcomp_west_side; + u32 control_srcomp_code_latch; + u32 control_pbiaslite; + u32 control_port_emif1_sdram_config; + u32 control_port_emif1_lpddr2_nvm_config; + u32 control_port_emif2_sdram_config; + u32 control_emif1_sdram_config_ext; + u32 control_emif2_sdram_config_ext; + u32 control_smart1nopmio_padconf_0; + u32 control_smart1nopmio_padconf_1; + u32 control_padconf_mode; + u32 control_xtal_oscillator; + u32 control_i2c_2; + u32 control_ckobuffer; + u32 control_wkup_control_spare_rw; + u32 control_wkup_control_spare_r; + u32 control_wkup_control_spare_r_c0; + u32 control_srcomp_east_side_wkup; + u32 control_efuse_1; + u32 control_efuse_2; + u32 control_efuse_3; + u32 control_efuse_4; + u32 control_efuse_5; + u32 control_efuse_6; + u32 control_efuse_7; + u32 control_efuse_8; + u32 control_efuse_9; + u32 control_efuse_10; + u32 control_efuse_11; + u32 control_efuse_12; + u32 control_efuse_13; +}; + struct dpll_params { u32 m; u32 n; @@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data *omap_vcores; extern const u32 sys_clk_array[8]; +extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const omap4_ctrl; +extern struct omap_sys_ctrl_regs const omap5_ctrl; void hw_data_init(void); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afd9b30..f34214b 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -50,18 +50,15 @@ static struct mmc hsmmc_dev[2]; static void omap4_vmmc_pbias_config(struct mmc *mmc) { u32 value = 0; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - - value = readl(&ctrl->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); - writel(value, &ctrl->control_pbiaslite); + writel(value, (*ctrl)->control_pbiaslite); /* set VMMC to 3V */ twl6030_power_mmc_init(); - value = readl(&ctrl->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; - writel(value, &ctrl->control_pbiaslite); + writel(value, (*ctrl)->control_pbiaslite); } #endif @@ -69,26 +66,24 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc) static void omap5_pbias_config(struct mmc *mmc) { u32 value = 0; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); value |= SDCARD_BIAS_HIZ_MODE; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); twl6035_mmc1_poweron_ldo(); - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); value &= ~SDCARD_BIAS_HIZ_MODE; value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); if (value & (1 << 23)) { value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); value |= SDCARD_BIAS_HIZ_MODE; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); } } #endif