From patchwork Thu Jan 31 05:51:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 217090 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 45BA42C008D for ; Thu, 31 Jan 2013 16:52:46 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F02844A195; Thu, 31 Jan 2013 06:52:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RG0E89y-f+RO; Thu, 31 Jan 2013 06:52:42 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B46424A14C; Thu, 31 Jan 2013 06:52:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF89C4A14B for ; Thu, 31 Jan 2013 06:52:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qTp19FT8Klyz for ; Thu, 31 Jan 2013 06:52:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 5926B4A129 for ; Thu, 31 Jan 2013 06:52:11 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0V5q8BI023342 for ; Wed, 30 Jan 2013 23:52:09 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0V5q7j7027917 for ; Thu, 31 Jan 2013 11:22:07 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Thu, 31 Jan 2013 11:22:07 +0530 Received: from localhost.localdomain (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0V5q5Po024468; Thu, 31 Jan 2013 11:22:06 +0530 From: R Sricharan To: Date: Thu, 31 Jan 2013 11:21:59 +0530 Message-ID: <1359611525-19017-2-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1359611525-19017-1-git-send-email-r.sricharan@ti.com> References: <1359611525-19017-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH 1/7] ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Lokesh Vutla Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 10 +++++++++- arch/arm/cpu/armv7/omap-common/emif-common.c | 21 +++++++++++++++++---- arch/arm/cpu/armv7/omap5/hwinit.c | 2 +- arch/arm/include/asm/emif.h | 6 ++++++ 4 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..0b818b8 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_BUILD /* @@ -299,7 +300,7 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else @@ -414,6 +415,13 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv) if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); + + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { + /* Configure LDO SRAM "magic" bits */ + writel(2, (*prcm)->prm_sldo_core_setup); + writel(2, (*prcm)->prm_sldo_mpu_setup); + writel(2, (*prcm)->prm_sldo_mm_setup); + } } static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 88253cf..8864abc 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -66,6 +66,19 @@ inline u32 emif_num(u32 base) return 0; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +u32 emif_sdram_type() +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { @@ -1079,7 +1092,7 @@ static void do_sdram_init(u32 base) * OPP to another) */ if (!(in_sdram || warm_reset())) { - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); else ddr3_init(base, regs); @@ -1264,7 +1277,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; - u32 omap_rev = omap_revision(); + u32 sdram_type = emif_sdram_type(); debug(">>sdram_init()\n"); @@ -1275,7 +1288,7 @@ void sdram_init(void) debug("in_sdram = %d\n", in_sdram); if (!(in_sdram || warm_reset())) { - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) bypass_dpll(&prcm->cm_clkmode_dpll_core); else writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); @@ -1298,7 +1311,7 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) freq_update_core(); /* Do some testing after the init */ diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d0c3ff7..4def422 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -191,7 +191,7 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); - if (omap_revision() <= OMAP5430_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); else io_settings_ddr3(); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index ed251ec..0824a80 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1027,6 +1027,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; @@ -1156,4 +1161,5 @@ extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); +u32 emif_sdram_type(void); #endif