From patchwork Thu Jan 31 00:06:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 217058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 735CC2C0086 for ; Thu, 31 Jan 2013 11:07:20 +1100 (EST) Comment: DKIM? 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Violators will be prosecuted; Wed, 30 Jan 2013 17:06:43 -0700 Received: from d03relay04.boulder.ibm.com (d03relay04.boulder.ibm.com [9.17.195.106]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 8C5C719D8042 for ; Wed, 30 Jan 2013 17:06:42 -0700 (MST) Received: from d03av06.boulder.ibm.com (d03av06.boulder.ibm.com [9.17.195.245]) by d03relay04.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r0V06gPd262950 for ; Wed, 30 Jan 2013 17:06:43 -0700 Received: from d03av06.boulder.ibm.com (loopback [127.0.0.1]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r0V092GG002452 for ; Wed, 30 Jan 2013 17:09:02 -0700 Received: from ibm-tiger.the-meissners.org ([9.33.37.85]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r0V0921j002446; Wed, 30 Jan 2013 17:09:02 -0700 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id DA62541D32; Wed, 30 Jan 2013 19:06:40 -0500 (EST) Date: Wed, 30 Jan 2013 19:06:40 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH], GCC 4.9 powerpc, merge movdi insns Message-ID: <20130131000640.GA17740@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13013100-7282-0000-0000-0000139ECED4 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This is the last of the merge insn patches. It merges the power6x movdi with the normal floating point movdi. 2013-01-30 Michael Meissner * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with movdi_internal64, using wg constraint for move direct operations. Like the other patches, I have bootstrapped with it, and had no regression changes. Once 4.9 opens up, is this acceptable to be checked in? Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 195592) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -8542,10 +8542,10 @@ (define_split [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) -(define_insn "*movdi_mfpgpr" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS +(define_insn "*movdi_internal64" + [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,?Z,?wa,?wa,r,*h,*h,?wa,r,?*wg") + (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,wa,Z,wa,*h,r,0,O,*wg,r"))] + "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" "@ @@ -8558,36 +8558,17 @@ (define_insn "*movdi_mfpgpr" stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 + stxsd%U0x %x1,%y0 + lxsd%U1x %x0,%y1 + xxlor %x0,%x1,%x1 mf%1 %0 mt%0 %1 nop + xxlxor %x0,%x0,%x0 mftgpr %0,%1 mffgpr %0,%1" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")]) - -(define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))] - "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DImode) - || gpc_reg_operand (operands[1], DImode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - li %0,%1 - lis %0,%v1 - # - stfd%U0%X0 %1,%0 - lfd%U1%X1 %0,%1 - fmr %0,%1 - mf%1 %0 - mt%0 %1 - nop - xxlxor %x0,%x0,%x0" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple") - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) + [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,fpstore,fpload,vecsimple,mfjmpr,mtjmpr,*,vecsimple,mftgpr,mffgpr") + (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4")]) ;; immediate value valid for a single instruction hiding in a const_double (define_insn ""