@@ -6326,6 +6326,34 @@
"mulhdu %0,%1,%2"
[(set_attr "type" "lmul")])
+(define_expand "mulditi3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
+ (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
+ "TARGET_POWERPC64"
+{
+ rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
+ emit_insn (gen_muldi3 (l, operands[1], operands[2]));
+ emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (DImode, operands[0]), l);
+ emit_move_insn (gen_highpart (DImode, operands[0]), h);
+ DONE;
+})
+
+(define_expand "umulditi3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
+ (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
+ "TARGET_POWERPC64"
+{
+ rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
+ emit_insn (gen_muldi3 (l, operands[1], operands[2]));
+ emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
+ emit_move_insn (gen_lowpart (DImode, operands[0]), l);
+ emit_move_insn (gen_highpart (DImode, operands[0]), h);
+ DONE;
+})
+
(define_insn "rotldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")