Patchwork [U-Boot,RFC] Add support for Boundary Devices Nitrogen6x boards

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Submitter Eric Nelson
Date Jan. 30, 2013, 6:10 p.m.
Message ID <1359569452-6556-2-git-send-email-eric.nelson@boundarydevices.com>
Download mbox | patch
Permalink /patch/216991/
State RFC
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Comments

Eric Nelson - Jan. 30, 2013, 6:10 p.m.
This patch adds support for the Nitrogen6X board(s) from
Boundary Devices. The boards are based on the i.MX6x
processor family with two major variants:	
	i.MX6Quad/6Dual
	i.MX6Dual-Lite/6Solo

More specifically, the board variations are:
       nitrogen6q              i.MX6Q/6D       1GB
       nitrogen6dl             i.MX6DL         1GB
       nitrogen6s              i.MX6S          512MB
       nitrogen6q2g            i.MX6Q/6D       2GB
       nitrogen6dl2g           i.MX6DL         2GB
       nitrogen6s1g            i.MX6S          1GB

Refer to http://boundarydevices.com/products/ for details.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 MAINTAINERS                                        |    8 +
 arch/arm/include/asm/arch-mx6/crm_regs.h           |   12 +
 arch/arm/include/asm/arch-mx6/iomux.h              |    5 +
 arch/arm/include/asm/arch-mx6/mx6-ddr.h            |   73 ++
 arch/arm/include/asm/arch-mx6/mx6dl-ddr.h          |   59 ++
 arch/arm/include/asm/arch-mx6/mx6dl_pins.h         |    3 +
 arch/arm/include/asm/arch-mx6/mx6q-ddr.h           |   57 ++
 board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg    |   37 +
 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg    |   37 +
 board/boundary/nitrogen6x/6x_bootscript.txt        |   58 ++
 .../boundary/nitrogen6x/6x_bootscript_android.txt  |   64 ++
 .../nitrogen6x/6x_bootscript_android_recovery.txt  |   64 ++
 board/boundary/nitrogen6x/6x_upgrade.txt           |   46 +
 board/boundary/nitrogen6x/800mhz_2x128mx16.cfg     |   37 +
 board/boundary/nitrogen6x/800mhz_2x256mx16.cfg     |   37 +
 board/boundary/nitrogen6x/800mhz_4x128mx16.cfg     |   37 +
 board/boundary/nitrogen6x/800mhz_4x256mx16.cfg     |   37 +
 board/boundary/nitrogen6x/Makefile                 |   41 +
 board/boundary/nitrogen6x/README                   |   93 ++
 board/boundary/nitrogen6x/clocks.cfg               |   31 +
 board/boundary/nitrogen6x/ddr-setup.cfg            |   94 ++
 board/boundary/nitrogen6x/nitrogen6dl.cfg          |   46 +
 board/boundary/nitrogen6x/nitrogen6dl2g.cfg        |   46 +
 board/boundary/nitrogen6x/nitrogen6q.cfg           |   46 +
 board/boundary/nitrogen6x/nitrogen6q2g.cfg         |   46 +
 board/boundary/nitrogen6x/nitrogen6s.cfg           |   46 +
 board/boundary/nitrogen6x/nitrogen6s1g.cfg         |   46 +
 board/boundary/nitrogen6x/nitrogen6x.c             |  901 ++++++++++++++++++++
 boards.cfg                                         |    6 +
 drivers/usb/host/ehci-mx6.c                        |    1 -
 include/configs/nitrogen6x.h                       |  284 ++++++
 31 files changed, 2397 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6-ddr.h
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6q-ddr.h
 create mode 100644 board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/6x_bootscript.txt
 create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android.txt
 create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
 create mode 100644 board/boundary/nitrogen6x/6x_upgrade.txt
 create mode 100644 board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
 create mode 100644 board/boundary/nitrogen6x/Makefile
 create mode 100644 board/boundary/nitrogen6x/README
 create mode 100644 board/boundary/nitrogen6x/clocks.cfg
 create mode 100644 board/boundary/nitrogen6x/ddr-setup.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6dl.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6dl2g.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6q.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6q2g.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6s.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6s1g.cfg
 create mode 100644 board/boundary/nitrogen6x/nitrogen6x.c
 create mode 100644 include/configs/nitrogen6x.h
Benoît Thébaudeau - Feb. 1, 2013, 8:02 p.m.
Hi Eric,

On Wednesday, January 30, 2013 7:10:52 PM, Eric Nelson wrote:
> This patch adds support for the Nitrogen6X board(s) from
> Boundary Devices. The boards are based on the i.MX6x
> processor family with two major variants:
> 	i.MX6Quad/6Dual
> 	i.MX6Dual-Lite/6Solo
> 
> More specifically, the board variations are:
>        nitrogen6q              i.MX6Q/6D       1GB
>        nitrogen6dl             i.MX6DL         1GB
>        nitrogen6s              i.MX6S          512MB
>        nitrogen6q2g            i.MX6Q/6D       2GB
>        nitrogen6dl2g           i.MX6DL         2GB
>        nitrogen6s1g            i.MX6S          1GB
> 
> Refer to http://boundarydevices.com/products/ for details.
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

You have probably already noticed it, but just to make sure you do not miss it,
my series about the i.MX6Q DDR3 init also affects this patch. And for the 6DL
and 6S variants, there is an equivalent change to make, translated to 400 MHz
(DDR3-800).

After a quick look at this patch, it looks good.

Best regards,
Benoît
Stefano Babic - Feb. 12, 2013, 9:12 a.m.
On 30/01/2013 19:10, Eric Nelson wrote:
> This patch adds support for the Nitrogen6X board(s) from
> Boundary Devices. The boards are based on the i.MX6x
> processor family with two major variants:	
> 	i.MX6Quad/6Dual
> 	i.MX6Dual-Lite/6Solo
> 
> More specifically, the board variations are:
>        nitrogen6q              i.MX6Q/6D       1GB
>        nitrogen6dl             i.MX6DL         1GB
>        nitrogen6s              i.MX6S          512MB
>        nitrogen6q2g            i.MX6Q/6D       2GB
>        nitrogen6dl2g           i.MX6DL         2GB
>        nitrogen6s1g            i.MX6S          1GB
> 
> Refer to http://boundarydevices.com/products/ for details.

Hi Eric,

some general comments in praparation your V2. I have only some minor points.

- Try to split your patch in several patches, if possible. The patch
covers different issues and the series will be easy to be review. This
is mainly for the changes outside boards/boundary - I know it is not
easy to split the rest.

- I agree you put your script in the board directory instead opf trying
to use CONFIG_EXTRA_ENV_SETTINGS.

- Agree with the split of the configuration data (clocks.cfg and ddr
setup). The same mechanism can be reused for other boards, too.

- and agree with the nomenclature. My +1 to rename mx6x_pins.h to
mx6q_pins.h as you suggest in the cover letter.

Regards,
Stefano Babic

> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> ---
>  MAINTAINERS                                        |    8 +
>  arch/arm/include/asm/arch-mx6/crm_regs.h           |   12 +
>  arch/arm/include/asm/arch-mx6/iomux.h              |    5 +
>  arch/arm/include/asm/arch-mx6/mx6-ddr.h            |   73 ++
>  arch/arm/include/asm/arch-mx6/mx6dl-ddr.h          |   59 ++
>  arch/arm/include/asm/arch-mx6/mx6dl_pins.h         |    3 +
>  arch/arm/include/asm/arch-mx6/mx6q-ddr.h           |   57 ++
>  board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg    |   37 +
>  board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg    |   37 +
>  board/boundary/nitrogen6x/6x_bootscript.txt        |   58 ++
>  .../boundary/nitrogen6x/6x_bootscript_android.txt  |   64 ++
>  .../nitrogen6x/6x_bootscript_android_recovery.txt  |   64 ++
>  board/boundary/nitrogen6x/6x_upgrade.txt           |   46 +
>  board/boundary/nitrogen6x/800mhz_2x128mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_2x256mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_4x128mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_4x256mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/Makefile                 |   41 +
>  board/boundary/nitrogen6x/README                   |   93 ++
>  board/boundary/nitrogen6x/clocks.cfg               |   31 +
>  board/boundary/nitrogen6x/ddr-setup.cfg            |   94 ++
>  board/boundary/nitrogen6x/nitrogen6dl.cfg          |   46 +
>  board/boundary/nitrogen6x/nitrogen6dl2g.cfg        |   46 +
>  board/boundary/nitrogen6x/nitrogen6q.cfg           |   46 +
>  board/boundary/nitrogen6x/nitrogen6q2g.cfg         |   46 +
>  board/boundary/nitrogen6x/nitrogen6s.cfg           |   46 +
>  board/boundary/nitrogen6x/nitrogen6s1g.cfg         |   46 +
>  board/boundary/nitrogen6x/nitrogen6x.c             |  901 ++++++++++++++++++++
>  boards.cfg                                         |    6 +
>  drivers/usb/host/ehci-mx6.c                        |    1 -
>  include/configs/nitrogen6x.h                       |  284 ++++++
>  31 files changed, 2397 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-mx6/mx6-ddr.h
>  create mode 100644 arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
>  create mode 100644 arch/arm/include/asm/arch-mx6/mx6q-ddr.h
>  create mode 100644 board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/6x_bootscript.txt
>  create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android.txt
>  create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
>  create mode 100644 board/boundary/nitrogen6x/6x_upgrade.txt
>  create mode 100644 board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
>  create mode 100644 board/boundary/nitrogen6x/Makefile
>  create mode 100644 board/boundary/nitrogen6x/README
>  create mode 100644 board/boundary/nitrogen6x/clocks.cfg
>  create mode 100644 board/boundary/nitrogen6x/ddr-setup.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6dl.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6dl2g.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6q.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6q2g.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6s.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6s1g.cfg
>  create mode 100644 board/boundary/nitrogen6x/nitrogen6x.c
>  create mode 100644 include/configs/nitrogen6x.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index faa9b5e..720beab 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1029,6 +1029,14 @@ Pali Rohár <pali.rohar@gmail.com>
>  
>  	nokia_rx51	ARM ARMV7 (OMAP34xx SoC)
>  
> +Eric Nelson <eric.nelson@boundarydevices.com>
> +	nitrogen6q		i.MX6Q/6D	1GB
> +	nitrogen6dl		i.MX6DL		1GB
> +	nitrogen6s		i.MX6S		512MB
> +	nitrogen6q2g    	i.MX6Q/6D	2GB
> +	nitrogen6dl2g		i.MX6DL		2GB
> +	nitrogen6s1g		i.MX6S		1GB
> +

Please maintain the list alphabetically sorted. I see that it last
entries were put unsorted, the issue was not seen.


>  -------------------------------------------------------------------------
>  
>  Unknown / orphaned boards:
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index d670f30..7676457 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -20,6 +20,17 @@
>  #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
>  
> +#define CCM_CCGR0		0x020C4068
> +#define CCM_CCGR1		0x020C406c
> +#define CCM_CCGR2		0x020C4070
> +#define CCM_CCGR3		0x020C4074
> +#define CCM_CCGR4		0x020C4078
> +#define CCM_CCGR5		0x020C407c
> +#define CCM_CCGR6		0x020C4080
> +
> +#define PMU_MISC2		0x020C8170
> +
> +#ifndef __ASSEMBLY__
>  struct mxc_ccm_reg {
>  	u32 ccr;	/* 0x0000 */

The 0x0000 comment is superfluous...

>  	u32 ccdr;
> @@ -105,6 +116,7 @@ struct mxc_ccm_reg {
>  	u32 analog_pfd_528_clr;
>  	u32 analog_pfd_528_tog;
>  };
> +#endif
>  
>  /* Define the bits in register CCR */
>  #define MXC_CCM_CCR_RBC_EN				(1 << 27)
> diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
> index d23abd7..57b514f 100644
> --- a/arch/arm/include/asm/arch-mx6/iomux.h
> +++ b/arch/arm/include/asm/arch-mx6/iomux.h
> @@ -16,6 +16,11 @@
>  
>  #ifndef __ASM_ARCH_IOMUX_H__
>  #define __ASM_ARCH_IOMUX_H__
> +
> +#define IOMUXC_GPR4		0x020e0010
> +#define IOMUXC_GPR6		0x020e0018
> +#define IOMUXC_GPR7		0x020e001c
> +
>  /*
>   * IOMUXC_GPR13 bit fields
>   */
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> new file mode 100644
> index 0000000..0a3cddc
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#ifndef __ASM_ARCH_MX6_DDR_H__
> +#define __ASM_ARCH_MX6_DDR_H__
> +
> +#ifdef CONFIG_MX6Q
> +#include "mx6q-ddr.h"
> +#else
> +#ifdef CONFIG_MX6DL
> +#include "mx6dl-ddr.h"
> +#else
> +#error "Please select cpu"
> +#endif	/* CONFIG_MX6DL */
> +#endif	/* CONFIG_MX6Q */

Ok for me.  We have discussed this way previously on ML.

> +
> +#define MMDC_P0_MDCTL		0x021b0000
> +#define MMDC_P0_MDPDC		0x021b0004
> +#define MMDC_P0_MDOTC		0x021b0008
> +#define MMDC_P0_MDCFG0		0x021b000c
> +#define MMDC_P0_MDCFG1		0x021b0010
> +#define MMDC_P0_MDCFG2		0x021b0014
> +#define MMDC_P0_MDMISC		0x021b0018
> +#define MMDC_P0_MDSCR		0x021b001c
> +#define MMDC_P0_MDREF		0x021b0020
> +#define MMDC_P0_MDRWD		0x021b002c
> +#define MMDC_P0_MDOR		0x021b0030
> +#define MMDC_P0_MDASP		0x021b0040
> +#define MMDC_P0_MAPSR		0x021b0404
> +#define MMDC_P0_MPZQHWCTRL	0x021b0800
> +#define MMDC_P0_MPWLDECTRL0	0x021b080c
> +#define MMDC_P0_MPWLDECTRL1	0x021b0810
> +#define MMDC_P0_MPODTCTRL	0x021b0818
> +#define MMDC_P0_MPRDDQBY0DL	0x021b081c
> +#define MMDC_P0_MPRDDQBY1DL	0x021b0820
> +#define MMDC_P0_MPRDDQBY2DL	0x021b0824
> +#define MMDC_P0_MPRDDQBY3DL	0x021b0828
> +#define MMDC_P0_MPDGCTRL0	0x021b083c
> +#define MMDC_P0_MPDGCTRL1	0x021b0840
> +#define MMDC_P0_MPRDDLCTL	0x021b0848
> +#define MMDC_P0_MPWRDLCTL	0x021b0850
> +#define MMDC_P0_MPMUR0		0x021b08b8
> +
> +#define MMDC_P1_MDCTL		0x021b4000
> +#define MMDC_P1_MDPDC		0x021b4004
> +#define MMDC_P1_MDOTC		0x021b4008
> +#define MMDC_P1_MDCFG0		0x021b400c
> +#define MMDC_P1_MDCFG1		0x021b4010
> +#define MMDC_P1_MDCFG2		0x021b4014
> +#define MMDC_P1_MDMISC		0x021b4018
> +#define MMDC_P1_MDSCR		0x021b401c
> +#define MMDC_P1_MDREF		0x021b4020
> +#define MMDC_P1_MDRWD		0x021b402c
> +#define MMDC_P1_MDOR		0x021b4030
> +#define MMDC_P1_MDASP		0x021b4040
> +#define MMDC_P1_MAPSR		0x021b4404
> +#define MMDC_P1_MPZQHWCTRL	0x021b4800
> +#define MMDC_P1_MPWLDECTRL0	0x021b480c
> +#define MMDC_P1_MPWLDECTRL1	0x021b4810
> +#define MMDC_P1_MPODTCTRL	0x021b4818
> +#define MMDC_P1_MPRDDQBY0DL	0x021b481c
> +#define MMDC_P1_MPRDDQBY1DL	0x021b4820
> +#define MMDC_P1_MPRDDQBY2DL	0x021b4824
> +#define MMDC_P1_MPRDDQBY3DL	0x021b4828
> +#define MMDC_P1_MPDGCTRL0	0x021b483c
> +#define MMDC_P1_MPDGCTRL1	0x021b4840
> +#define MMDC_P1_MPRDDLCTL	0x021b4848
> +#define MMDC_P1_MPWRDLCTL	0x021b4850
> +#define MMDC_P1_MPMUR0		0x021b48b8
> +
> +#endif	/*__ASM_ARCH_MX6_DDR_H__ */
> diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
> new file mode 100644
> index 0000000..5a4bfc6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#ifndef __ASM_ARCH_MX6DLS_DDR_H__
> +#define __ASM_ARCH_MX6DLS_DDR_H__
> +
> +#ifndef CONFIG_MX6DL
> +#ifndef CONFIG_MX6S
> +#error "wrong CPU"
> +#endif
> +#endif
> +
> +#define IOM_DRAM_DQM0		0x020e0470
> +#define IOM_DRAM_DQM1		0x020e0474
> +#define IOM_DRAM_DQM2		0x020e0478
> +#define IOM_DRAM_DQM3		0x020e047c
> +#define IOM_DRAM_DQM4		0x020e0480
> +#define IOM_DRAM_DQM5		0x020e0484
> +#define IOM_DRAM_DQM6		0x020e0488
> +#define IOM_DRAM_DQM7		0x020e048c
> +
> +#define IOM_DRAM_CAS		0x020e0464
> +#define IOM_DRAM_RAS		0x020e0490
> +#define IOM_DRAM_RESET		0x020e0494
> +#define IOM_DRAM_SDCLK_0	0x020e04ac
> +#define IOM_DRAM_SDCLK_1	0x020e04b0
> +#define IOM_DRAM_SDBA2		0x020e04a0
> +#define IOM_DRAM_SDCKE0		0x020e04a4
> +#define IOM_DRAM_SDCKE1		0x020e04a8
> +#define IOM_DRAM_SDODT0		0x020e04b4
> +#define IOM_DRAM_SDODT1		0x020e04b8
> +
> +#define IOM_DRAM_SDQS0		0x020e04bc
> +#define IOM_DRAM_SDQS1		0x020e04c0
> +#define IOM_DRAM_SDQS2		0x020e04c4
> +#define IOM_DRAM_SDQS3		0x020e04c8
> +#define IOM_DRAM_SDQS4		0x020e04cc
> +#define IOM_DRAM_SDQS5		0x020e04d0
> +#define IOM_DRAM_SDQS6		0x020e04d4
> +#define IOM_DRAM_SDQS7		0x020e04d8
> +
> +#define IOM_GRP_B0DS		0x020e0764
> +#define IOM_GRP_B1DS		0x020e0770
> +#define IOM_GRP_B2DS		0x020e0778
> +#define IOM_GRP_B3DS		0x020e077c
> +#define IOM_GRP_B4DS		0x020e0780
> +#define IOM_GRP_B5DS		0x020e0784
> +#define IOM_GRP_B6DS		0x020e078c
> +#define IOM_GRP_B7DS		0x020e0748
> +#define IOM_GRP_ADDDS		0x020e074c
> +#define IOM_DDRMODE_CTL		0x020e0750
> +#define IOM_GRP_DDRPKE		0x020e0754
> +#define IOM_GRP_DDRMODE		0x020e0760
> +#define IOM_GRP_CTLDS		0x020e076c
> +#define IOM_GRP_DDR_TYPE	0x020e0774
> +
> +#endif	/*__ASM_ARCH_MX6S_DDR_H__ */
> diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> index 79e2c4f..9b9c571 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
> @@ -105,6 +105,9 @@ enum {
>  	MX6DL_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
>  	MX6DL_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
>  	MX6DL_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
> +	MX6DL_PAD_NANDF_CS1__GPIO_6_14		= IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
> +	MX6DL_PAD_NANDF_CS2__GPIO_6_15		= IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
> +	MX6DL_PAD_NANDF_CS3__GPIO_6_16		= IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
>  	MX6DL_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
>  	MX6DL_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
>  	MX6DL_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
> diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
> new file mode 100644
> index 0000000..4060600
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
> @@ -0,0 +1,57 @@
> +/*
> + * Copyright (C) 2012 Boundary Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +#ifndef __ASM_ARCH_MX6Q_DDR_H__
> +#define __ASM_ARCH_MX6Q_DDR_H__
> +
> +#ifndef CONFIG_MX6Q
> +#error "wrong CPU"
> +#endif
> +
> +#define IOM_DRAM_DQM0		0x020e05ac
> +#define IOM_DRAM_DQM1		0x020e05b4
> +#define IOM_DRAM_DQM2		0x020e0528
> +#define IOM_DRAM_DQM3		0x020e0520
> +#define IOM_DRAM_DQM4		0x020e0514
> +#define IOM_DRAM_DQM5		0x020e0510
> +#define IOM_DRAM_DQM6		0x020e05bc
> +#define IOM_DRAM_DQM7		0x020e05c4
> +
> +#define IOM_DRAM_CAS		0x020e056c
> +#define IOM_DRAM_RAS		0x020e0578
> +#define IOM_DRAM_RESET		0x020e057c
> +#define IOM_DRAM_SDCLK_0	0x020e0588
> +#define IOM_DRAM_SDCLK_1	0x020e0594
> +#define IOM_DRAM_SDBA2		0x020e058c
> +#define IOM_DRAM_SDCKE0		0x020e0590
> +#define IOM_DRAM_SDCKE1		0x020e0598
> +#define IOM_DRAM_SDODT0		0x020e059c
> +#define IOM_DRAM_SDODT1		0x020e05a0
> +
> +#define IOM_DRAM_SDQS0		0x020e05a8
> +#define IOM_DRAM_SDQS1		0x020e05b0
> +#define IOM_DRAM_SDQS2		0x020e0524
> +#define IOM_DRAM_SDQS3		0x020e051c
> +#define IOM_DRAM_SDQS4		0x020e0518
> +#define IOM_DRAM_SDQS5		0x020e050c
> +#define IOM_DRAM_SDQS6		0x020e05b8
> +#define IOM_DRAM_SDQS7		0x020e05c0
> +
> +#define IOM_GRP_B0DS		0x020e0784
> +#define IOM_GRP_B1DS		0x020e0788
> +#define IOM_GRP_B2DS		0x020e0794
> +#define IOM_GRP_B3DS		0x020e079c
> +#define IOM_GRP_B4DS		0x020e07a0
> +#define IOM_GRP_B5DS		0x020e07a4
> +#define IOM_GRP_B6DS		0x020e07a8
> +#define IOM_GRP_B7DS		0x020e0748
> +#define IOM_GRP_ADDDS		0x020e074c
> +#define IOM_DDRMODE_CTL		0x020e0750
> +#define IOM_GRP_DDRPKE		0x020e0758
> +#define IOM_GRP_DDRMODE		0x020e0774
> +#define IOM_GRP_CTLDS		0x020e078c
> +#define IOM_GRP_DDR_TYPE	0x020e0798
> +
> +#endif	/*__ASM_ARCH_MX6Q_DDR_H__ */
> diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
> new file mode 100644
> index 0000000..63fb31d
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x00020036
> +DATA 4, MMDC_P0_MDCFG0, 0x555A7975
> +DATA 4, MMDC_P0_MDCFG1, 0xFF538E64
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x09444040
> +DATA 4, MMDC_P0_MDPDC, 0x00025576
> +DATA 4, MMDC_P0_MDASP, 0x00000027
> +DATA 4, MMDC_P0_MDCTL, 0x831A0000
> +DATA 4, MMDC_P0_MDSCR, 0x04088032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00428031
> +DATA 4, MMDC_P0_MDSCR, 0x09408030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00005800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x434B0350
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x034C0359
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x434B0350
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x03650348
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4436383B
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x39393341
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x35373933
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x48254A36
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x001F001F
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x001F001F
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x00440044
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x00440044
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
> new file mode 100644
> index 0000000..68e70ad
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x00020036
> +DATA 4, MMDC_P0_MDCFG0, 0x895A7975
> +DATA 4, MMDC_P0_MDCFG1, 0xFF538E64
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x09444040
> +DATA 4, MMDC_P0_MDPDC, 0x00025576
> +DATA 4, MMDC_P0_MDASP, 0x00000047
> +DATA 4, MMDC_P0_MDCTL, 0x841A0000
> +DATA 4, MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00428031
> +DATA 4, MMDC_P0_MDSCR, 0x09408030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00007800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x43040319
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x03040279
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x43040321
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x03030251
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4d434248
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x42413c4d
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x34424543
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x49324933
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x001a0017
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x001F001F
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x00170027
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x000a001f
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt
> new file mode 100644
> index 0000000..fe75976
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/6x_bootscript.txt
> @@ -0,0 +1,58 @@
> +setenv bootargs enable_wait_mode=off
> +setenv nextcon 0;
> +
> +if hdmidet ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
> +	setenv fbmem "fbmem=28M";
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no HDMI monitor";
> +fi
> +
> +i2c dev 2
> +if i2c probe 0x04 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbmem "fbmem=10M";
> +	else
> +		setenv fbmem ${fbmem},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no Freescale display";
> +fi
> +
> +if i2c probe 0x38 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbmem "fbmem=10M";
> +	else
> +		setenv fbmem ${fbmem},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 1024x600 display";
> +fi
> +
> +if i2c probe 0x48 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbmem "fbmem=10M";
> +	else
> +		setenv fbmem ${fbmem},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 800x480 display";
> +fi
> +
> +while test "3" -ne $nextcon ; do
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
> +	setexpr nextcon $nextcon + 1 ;
> +done
> +
> +setenv bootargs $bootargs $fbmem
> +
> +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M root=/dev/mmcblk0p1 rootwait consoleblank=0 ;
> +${fs}load mmc ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; echo "Error loading kernel image"
> +
> diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt
> new file mode 100644
> index 0000000..7ade2e5
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt
> @@ -0,0 +1,64 @@
> +${dtype} dev ${disk}
> +
> +setenv bootargs enable_wait_mode=off
> +setenv nextcon 0;
> +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
> +
> +i2c dev 2
> +
> +if i2c probe 0x04 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no Freescale display";
> +fi
> +
> +if i2c probe 0x38 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 1024x600 display";
> +fi
> +
> +if i2c probe 0x48 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 800x480 display";
> +fi
> +
> +if hdmidet ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=28M";
> +	else
> +		setenv fbcon ${fbcon},28M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no HDMI monitor";
> +fi
> +
> +while test "3" -ne $nextcon ; do
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
> +	setexpr nextcon $nextcon + 1 ;
> +done
> +
> +setenv bootargs $bootargs fbcon=$fbcon
> +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000; echo "Error loading kernel image"
> +
> diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
> new file mode 100644
> index 0000000..7ade2e5
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
> @@ -0,0 +1,64 @@
> +${dtype} dev ${disk}
> +
> +setenv bootargs enable_wait_mode=off
> +setenv nextcon 0;
> +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
> +
> +i2c dev 2
> +
> +if i2c probe 0x04 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no Freescale display";
> +fi
> +
> +if i2c probe 0x38 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 1024x600 display";
> +fi
> +
> +if i2c probe 0x48 ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=10M";
> +	else
> +		setenv fbcon ${fbcon},10M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no 800x480 display";
> +fi
> +
> +if hdmidet ; then
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
> +	if test "0" -eq $nextcon; then
> +		setenv fbcon "fbcon=28M";
> +	else
> +		setenv fbcon ${fbcon},28M
> +	fi
> +	setexpr nextcon $nextcon + 1
> +else
> +	echo "------ no HDMI monitor";
> +fi
> +
> +while test "3" -ne $nextcon ; do
> +	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
> +	setexpr nextcon $nextcon + 1 ;
> +done
> +
> +setenv bootargs $bootargs fbcon=$fbcon
> +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000; echo "Error loading kernel image"
> +
> diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
> new file mode 100644
> index 0000000..354d1a2
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/6x_upgrade.txt
> @@ -0,0 +1,46 @@
> +setenv stdout serial,vga
> +echo "check U-Boot" ;
> +setenv offset 0x400
> +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
> +      echo "read $filesize bytes from SD card" ;
> +      if sf probe || sf probe || \
> +	 sf probe 1 27000000 || sf probe 1 27000000 ; then
> +	   echo "probed SPI ROM" ;
> +           if sf read 0x12400000 $offset $filesize ; then
> +               if cmp.b 0x12000000 0x12400000 $filesize ; then
> +                   echo "------- U-Boot versions match" ;
> +               else
> +                   echo "Need U-Boot upgrade" ;
> +                   echo "Program in 5 seconds" ;
> +                   for n in 5 4 3 2 1 ; do
> +                        echo $n ;
> +                        sleep 1 ;
> +                   done
> +		   echo "erasing" ;
> +                   sf erase 0 0x50000 ;
> +		   # two steps to prevent bricking
> +		   echo "programming" ;
> +                   sf write 0x12000000 $offset $filesize ;
> +		   echo "verifying" ;
> +                   if sf read 0x12400000 $offset $filesize ; then
> +                       if cmp.b 0x12000000 0x12400000 $filesize ; then
> +                           while echo "---- U-Boot upgraded. reset" ; do
> +				sleep 120
> +			   done
> +                       else
> +                           echo "Read verification error" ;
> +                       fi
> +                   else
> +                        echo "Error re-reading EEPROM" ;
> +                   fi
> +               fi
> +           else
> +               echo "Error reading boot loader from EEPROM" ;
> +           fi
> +      else
> +           echo "Error initializing EEPROM" ;
> +      fi ;
> +else
> +     echo "No U-Boot image found on SD card" ;
> +fi
> +
> diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
> new file mode 100644
> index 0000000..ffd1078
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x0002002D
> +DATA 4, MMDC_P0_MDCFG0, 0x696D5323
> +DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x00333030
> +DATA 4, MMDC_P0_MDPDC, 0x0002556D
> +DATA 4, MMDC_P0_MDASP, 0x00000017
> +DATA 4, MMDC_P0_MDCTL, 0x83190000
> +DATA 4, MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00048031
> +DATA 4, MMDC_P0_MDSCR, 0x07208030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00005800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
> new file mode 100644
> index 0000000..35b38b7
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x0002002D
> +DATA 4, MMDC_P0_MDCFG0, 0x696D5323
> +DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x00333030
> +DATA 4, MMDC_P0_MDPDC, 0x0002556D
> +DATA 4, MMDC_P0_MDASP, 0x00000027
> +DATA 4, MMDC_P0_MDCTL, 0x84190000
> +DATA 4, MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00048031
> +DATA 4, MMDC_P0_MDSCR, 0x07208030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00007800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
> new file mode 100644
> index 0000000..76ae7e9
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x0002002D
> +DATA 4, MMDC_P0_MDCFG0, 0x696D5323
> +DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x00333030
> +DATA 4, MMDC_P0_MDPDC, 0x0002556D
> +DATA 4, MMDC_P0_MDASP, 0x00000027
> +DATA 4, MMDC_P0_MDCTL, 0x831A0000
> +DATA 4, MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00048031
> +DATA 4, MMDC_P0_MDSCR, 0x07208030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00005800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
> new file mode 100644
> index 0000000..8de937c
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
> @@ -0,0 +1,37 @@
> +DATA 4, MMDC_P0_MDPDC, 0x0002002D
> +DATA 4, MMDC_P0_MDCFG0, 0x696D5323
> +DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
> +DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
> +DATA 4, MMDC_P0_MDRWD, 0x000026D2
> +DATA 4, MMDC_P0_MDOR, 0x005B0E21
> +DATA 4, MMDC_P0_MDOTC, 0x00333030
> +DATA 4, MMDC_P0_MDPDC, 0x0002556D
> +DATA 4, MMDC_P0_MDASP, 0x00000047
> +DATA 4, MMDC_P0_MDCTL, 0x841A0000
> +DATA 4, MMDC_P0_MDSCR, 0x04008032
> +DATA 4, MMDC_P0_MDSCR, 0x00008033
> +DATA 4, MMDC_P0_MDSCR, 0x00048031
> +DATA 4, MMDC_P0_MDSCR, 0x07208030
> +DATA 4, MMDC_P0_MDSCR, 0x04008040
> +DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
> +DATA 4, MMDC_P0_MDREF, 0x00007800
> +DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
> +DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
> +DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
> +DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
> +DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
> +DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
> +DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
> +DATA 4, MMDC_P0_MPMUR0, 0x00000800
> +DATA 4, MMDC_P1_MPMUR0, 0x00000800
> +DATA 4, MMDC_P0_MDSCR, 0x00000000
> +DATA 4, MMDC_P0_MAPSR, 0x00011006
> +
> diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
> new file mode 100644
> index 0000000..63da7d0
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/Makefile
> @@ -0,0 +1,41 @@
> +#
> +# Copyright (C) 2012, Guennadi Liakhovetski <lg@denx.de>
> +#
> +# (C) Copyright 2012 Freescale Semiconductor, Inc.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB    = $(obj)lib$(BOARD).o
> +
> +COBJS  := nitrogen6x.o
> +
> +SRCS   := $(COBJS:.o=.c)
> +OBJS   := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB):        $(obj).depend $(OBJS)
> +	$(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README
> new file mode 100644
> index 0000000..330cb49
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/README
> @@ -0,0 +1,93 @@
> +U-Boot for the Boundary Devices Nitrogen6X and
> +Freescale i.MX6Q SabreLite boards
> +
> +This file contains information for the port of
> +U-Boot to the Boundary Devices Nitrogen6X and
> +Freescale i.MX6Q SabreLite boards.
> +
> +1. Boot source, boot from SPI NOR
> +---------------------------------
> +The configuration in this directory supports both the
> +Nitrogen6X and Freescale SabreLite board, but in a
> +different fashion from Freescale's implementation in
> +board/freescale/mx6qsabrelite.
> +
> +In particular, this image supports booting from SPI NOR
> +and saving the environment to SPI NOR.
> +
> +It does not support 'boot from SD' at offset 0x400
> +except through the 'bmode' command.
> +	http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
> +
> +2. Boots using 6x_bootscript on SATA or SD card
> +-----------------------------------------------
> +The default bootcmd for these boards is configured
> +to look for and source a boot script named '6x_bootscript'
> +in the root of the first partition of the following
> +devices:
> +
> +	sata 0
> +	mmc 0
> +	mmc 1
> +
> +They're searched in the order listed above, trying both the
> +ext2 and fat filesystems.
> +
> +2. Maintaining the SPI NOR
> +--------------------------
> +A couple of convenience commands
> +
> +	clearenv - clear environment to factory default
> +	upgradeu - look and source a boot script named
> +		'6x_upgrade' to upgrade the U-Boot version
> +		in SPI NOR. The search is the same as for
> +		6x_bootscript described above.
> +
> +3. Display support
> +------------------
> +U-Boot support for the following displays is configured by
> +default:
> +
> +    HDMI           - 1024 x 768 for maximum compatibility
> +    Hannstar-XGA   - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
> +    wsvga-lvds     - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
> +    wvga-rgb       - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
> +
> +Since the ipuv3_fb display driver currently supports only a single display,
> +this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
> +or the I2C touch controller of the LVDS and RGB displays in the priority
> +listed above.
> +
> +Setting 'panel' environment variable to one of the names above will
> +override auto-detection and force activation of the specified panel.
> +
> +4. Building
> +------------
> +
> +To build U-Boot for one of the Nitrogen6x or SabreLite board:
> +
> +	make nitrogen6x_config
> +	make u-boot.imx
> +
> +Note that 'nitrogen6x' is a placeholder. The complete list of supported
> +board configurations is shown in tha MAINTAINERS file:
> +	nitrogen6q		i.MX6Q/6D	1GB
> +	nitrogen6dl		i.MX6DL		1GB
> +	nitrogen6s		i.MX6S		512MB
> +	nitrogen6q2g    	i.MX6Q/6D	2GB
> +	nitrogen6dl2g		i.MX6DL		2GB
> +	nitrogen6s1g		i.MX6S		1GB
> +
> +The -6q variants support either the i.MX6Quad or i.MX6Dual processors
> +and are configured for a 64-bit memory bus at 1066 MHz.
> +
> +The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
> +
> +The -6s variants use a 32-bit memory bus at 800MHz.
> +
> +If you place the u-boot.imx into a single-partition SD card
> +along with a binary version of the boot script 6x_upgrade.txt,
> +you can program it using 'upgradeu':
> +
> +	U-Boot> run upgradeu
> +
> diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
> new file mode 100644
> index 0000000..5143b78
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/clocks.cfg
> @@ -0,0 +1,31 @@
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type           Address        Value
> + *
> + * where:
> + *      Addr-type register length (1,2 or 4 bytes)
> + *      Address   absolute address of the register
> + *      value     value to be stored in the register
> + */
> +
> +/* set the default clock gate to save power */
> +DATA 4, CCM_CCGR0, 0x00C03F3F
> +DATA 4, CCM_CCGR1, 0x0030FC03
> +DATA 4, CCM_CCGR2, 0x0FFFC000
> +DATA 4, CCM_CCGR3, 0x3FF00000
> +DATA 4, CCM_CCGR4, 0x00FFF300
> +DATA 4, CCM_CCGR5, 0x0F0000C3
> +DATA 4, CCM_CCGR6, 0x000003FF
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4, IOMUXC_GPR4, 0xF00000CF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +DATA 4, IOMUXC_GPR6, 0x007F007F
> +DATA 4, IOMUXC_GPR7, 0x007F007F
> +
> +/* Set LDO Ramp rates to fast */
> +/* 64 clocks/0.266uS/25mV */
> +/* == 32uS for 0.95->1.25V */
> +DATA 4, PMU_MISC2, 0x00670f67
> diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
> new file mode 100644
> index 0000000..b3f7ec4
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/ddr-setup.cfg
> @@ -0,0 +1,94 @@
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type           Address        Value
> + *
> + * where:
> + *      Addr-type register length (1,2 or 4 bytes)
> + *      Address   absolute address of the register
> + *      value     value to be stored in the register
> + */
> +
> +/*
> + * DDR3 settings
> + * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
> + *	   memory bus width: 64 bits	x16/x32/x64
> + * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
> + *	   memory bus width: 64 bits	x16/x32/x64
> + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
> + *	   memory bus width: 32 bits	x16/x32
> + */
> +DATA 4, IOM_DRAM_SDQS0, 0x00000030
> +DATA 4, IOM_DRAM_SDQS1, 0x00000030
> +DATA 4, IOM_DRAM_SDQS2, 0x00000030
> +DATA 4, IOM_DRAM_SDQS3, 0x00000030
> +DATA 4, IOM_DRAM_SDQS4, 0x00000030
> +DATA 4, IOM_DRAM_SDQS5, 0x00000030
> +DATA 4, IOM_DRAM_SDQS6, 0x00000030
> +DATA 4, IOM_DRAM_SDQS7, 0x00000030
> +
> +DATA 4, IOM_GRP_B0DS, 0x00000030
> +DATA 4, IOM_GRP_B1DS, 0x00000030
> +DATA 4, IOM_GRP_B2DS, 0x00000030
> +DATA 4, IOM_GRP_B3DS, 0x00000030
> +DATA 4, IOM_GRP_B4DS, 0x00000030
> +DATA 4, IOM_GRP_B5DS, 0x00000030
> +DATA 4, IOM_GRP_B6DS, 0x00000030
> +DATA 4, IOM_GRP_B7DS, 0x00000030
> +DATA 4, IOM_GRP_ADDDS, 0x00000030
> +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
> +DATA 4, IOM_GRP_CTLDS, 0x00000030
> +
> +DATA 4, IOM_DRAM_DQM0, 0x00020030
> +DATA 4, IOM_DRAM_DQM1, 0x00020030
> +DATA 4, IOM_DRAM_DQM2, 0x00020030
> +DATA 4, IOM_DRAM_DQM3, 0x00020030
> +DATA 4, IOM_DRAM_DQM4, 0x00020030
> +DATA 4, IOM_DRAM_DQM5, 0x00020030
> +DATA 4, IOM_DRAM_DQM6, 0x00020030
> +DATA 4, IOM_DRAM_DQM7, 0x00020030
> +
> +DATA 4, IOM_DRAM_CAS, 0x00020030
> +DATA 4, IOM_DRAM_RAS, 0x00020030
> +DATA 4, IOM_DRAM_SDCLK_0, 0x00020030
> +DATA 4, IOM_DRAM_SDCLK_1, 0x00020030
> +
> +DATA 4, IOM_DRAM_RESET, 0x000e0030
> +DATA 4, IOM_DRAM_SDCKE0, 0x00003000
> +DATA 4, IOM_DRAM_SDCKE1, 0x00003000
> +
> +DATA 4, IOM_DRAM_SDODT0, 0x00003030
> +DATA 4, IOM_DRAM_SDODT1, 0x00003030
> +
> +/* (differential input) */
> +DATA 4, IOM_DDRMODE_CTL, 0x00020000
> +/* (differential input) */
> +DATA 4, IOM_GRP_DDRMODE, 0x00020000
> +/* disable ddr pullups */
> +DATA 4, IOM_GRP_DDRPKE, 0x00000000
> +DATA 4, IOM_DRAM_SDBA2, 0x00000000
> +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
> +DATA 4, IOM_GRP_DDR_TYPE, 0x000C0000
> +
> +/* Read data DQ Byte0-3 delay */
> +DATA 4, MMDC_P0_MPRDDQBY0DL, 0x33333333
> +DATA 4, MMDC_P0_MPRDDQBY1DL, 0x33333333
> +DATA 4, MMDC_P0_MPRDDQBY2DL, 0x33333333
> +DATA 4, MMDC_P0_MPRDDQBY3DL, 0x33333333
> +DATA 4, MMDC_P1_MPRDDQBY0DL, 0x33333333
> +DATA 4, MMDC_P1_MPRDDQBY1DL, 0x33333333
> +DATA 4, MMDC_P1_MPRDDQBY2DL, 0x33333333
> +DATA 4, MMDC_P1_MPRDDQBY3DL, 0x33333333
> +
> +/*
> + * MDMISC	mirroring	interleaved (row/bank/col)
> + */
> +DATA 4, MMDC_P0_MDMISC, 0x00081740
> +
> +/*
> + * MDSCR	con_req
> + */
> +DATA 4, MMDC_P0_MDSCR, 0x00008000
> +
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
> new file mode 100644
> index 0000000..60300c5
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "800mhz_4x128mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
> new file mode 100644
> index 0000000..b62c73e
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "800mhz_4x256mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
> new file mode 100644
> index 0000000..30353a5
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "1066mhz_4x128mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
> new file mode 100644
> index 0000000..8c1a74f
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "1066mhz_4x256mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
> new file mode 100644
> index 0000000..8a73a51
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "800mhz_2x128mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
> new file mode 100644
> index 0000000..3659e1e
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright (C) 2013 Boundary Devices
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not write to the Free Software
> + * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> + * MA 02110-1301 USA
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +/* image version */
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi, sd (the board has no nand neither onenand)
> + */
> +BOOT_FROM      sd
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +#include "asm/arch/mx6-ddr.h"
> +#include "asm/arch/iomux.h"
> +#include "asm/arch/crm_regs.h"
> +
> +#include "ddr-setup.cfg"
> +#include "800mhz_2x256mx16.cfg"
> +#include "clocks.cfg"
> +
> diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
> new file mode 100644
> index 0000000..9e3898a
> --- /dev/null
> +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> @@ -0,0 +1,901 @@
> +/*
> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#ifdef CONFIG_MX6Q
> +#include <asm/arch/mx6x_pins.h>
> +#else
> +#ifdef CONFIG_MX6DL
> +#include <asm/arch/mx6dl_pins.h>
> +#define FOR_DL_SOLO
> +#else
> +#ifdef CONFIG_MX6S
> +#include <asm/arch/mx6dl_pins.h>
> +#define FOR_DL_SOLO
> +#else
> +#error "Please select cpu"
> +#endif	/* CONFIG_MX6S */
> +#endif	/* CONFIG_MX6DL */
> +#endif	/* CONFIG_MX6Q */
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <micrel.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <linux/fb.h>
> +#include <ipu_pixfmt.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <i2c.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef FOR_DL_SOLO
> +#define MX6PAD(a) MX6DL_PAD_##a
> +#else
> +#define MX6PAD(a) MX6Q_PAD_##a
> +#endif
> +
> +#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
> +	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
> +	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
> +	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> +
> +#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
> +	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
> +	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
> +	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
> +
> +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
> +	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
> +
> +#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
> +	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
> +	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> +
> +#define WEAK_PULLUP	(PAD_CTL_PKE | PAD_CTL_PUE |		\
> +	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
> +	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
> +	PAD_CTL_SRE_SLOW)
> +
> +#define WEAK_PULLDOWN	(PAD_CTL_PKE | PAD_CTL_PUE |		\
> +	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
> +	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
> +	PAD_CTL_SRE_SLOW)
> +
> +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
> +
> +int dram_init(void)
> +{
> +	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +
> +	return 0;
> +}
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> +	MX6PAD(SD3_DAT6__UART1_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6PAD(SD3_DAT7__UART1_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart2_pads[] = {
> +	MX6PAD(EIM_D26__UART2_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MX6PAD(EIM_D27__UART2_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +
> +/* I2C1, SGTL5000 */
> +struct i2c_pads_info i2c_pad_info0 = {
> +	.scl = {
> +		.i2c_mode = MX6PAD(EIM_D21__I2C1_SCL) | PC,
> +		.gpio_mode = MX6PAD(EIM_D21__GPIO_3_21) | PC,
> +		.gp = IMX_GPIO_NR(3, 21)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6PAD(EIM_D28__I2C1_SDA) | PC,
> +		.gpio_mode = MX6PAD(EIM_D28__GPIO_3_28) | PC,
> +		.gp = IMX_GPIO_NR(3, 28)
> +	}
> +};
> +
> +/* I2C2 Camera, MIPI */
> +struct i2c_pads_info i2c_pad_info1 = {
> +	.scl = {
> +		.i2c_mode = MX6PAD(KEY_COL3__I2C2_SCL) | PC,
> +		.gpio_mode = MX6PAD(KEY_COL3__GPIO_4_12) | PC,
> +		.gp = IMX_GPIO_NR(4, 12)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6PAD(KEY_ROW3__I2C2_SDA) | PC,
> +		.gpio_mode = MX6PAD(KEY_ROW3__GPIO_4_13) | PC,
> +		.gp = IMX_GPIO_NR(4, 13)
> +	}
> +};
> +
> +/* I2C3, J15 - RGB connector */
> +struct i2c_pads_info i2c_pad_info2 = {
> +	.scl = {
> +		.i2c_mode = MX6PAD(GPIO_5__I2C3_SCL) | PC,
> +		.gpio_mode = MX6PAD(GPIO_5__GPIO_1_5) | PC,
> +		.gp = IMX_GPIO_NR(1, 5)
> +	},
> +	.sda = {
> +		.i2c_mode = MX6PAD(GPIO_16__I2C3_SDA) | PC,
> +		.gpio_mode = MX6PAD(GPIO_16__GPIO_7_11) | PC,
> +		.gp = IMX_GPIO_NR(7, 11)
> +	}
> +};
> +
> +iomux_v3_cfg_t const usdhc3_pads[] = {
> +	MX6PAD(SD3_CLK__USDHC3_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_CMD__USDHC3_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_DAT0__USDHC3_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_DAT1__USDHC3_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_DAT2__USDHC3_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_DAT3__USDHC3_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD3_DAT5__GPIO_7_0)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
> +};
> +
> +iomux_v3_cfg_t const usdhc4_pads[] = {
> +	MX6PAD(SD4_CLK__USDHC4_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD4_CMD__USDHC4_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD4_DAT0__USDHC4_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD4_DAT1__USDHC4_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD4_DAT2__USDHC4_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(SD4_DAT3__USDHC4_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	MX6PAD(NANDF_D6__GPIO_2_6)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
> +};
> +
> +iomux_v3_cfg_t const enet_pads1[] = {
> +	MX6PAD(ENET_MDIO__ENET_MDIO)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(ENET_MDC__ENET_MDC)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TXC__ENET_RGMII_TXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TD0__ENET_RGMII_TD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TD1__ENET_RGMII_TD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TD2__ENET_RGMII_TD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TD3__ENET_RGMII_TD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_TX_CTL__RGMII_TX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(ENET_REF_CLK__ENET_TX_CLK)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	/* pin 35 - 1 (PHY_AD2) on reset */
> +	MX6PAD(RGMII_RXC__GPIO_6_30)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 32 - 1 - (MODE0) all */
> +	MX6PAD(RGMII_RD0__GPIO_6_25)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 31 - 1 - (MODE1) all */
> +	MX6PAD(RGMII_RD1__GPIO_6_27)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 28 - 1 - (MODE2) all */
> +	MX6PAD(RGMII_RD2__GPIO_6_28)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 27 - 1 - (MODE3) all */
> +	MX6PAD(RGMII_RD3__GPIO_6_29)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
> +	MX6PAD(RGMII_RX_CTL__GPIO_6_24)	| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	/* pin 42 PHY nRST */
> +	MX6PAD(EIM_D23__GPIO_3_23)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +	MX6PAD(ENET_RXD0__GPIO_1_27)		| MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet_pads2[] = {
> +	MX6PAD(RGMII_RXC__ENET_RGMII_RXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_RD0__ENET_RGMII_RD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_RD1__ENET_RGMII_RD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_RD2__ENET_RGMII_RD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_RD3__ENET_RGMII_RD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MX6PAD(RGMII_RX_CTL__RGMII_RX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +/* wl1271 pads on nitrogen6x */
> +iomux_v3_cfg_t const wl12xx_pads[] = {
> +	(MX6PAD(NANDF_CS1__GPIO_6_14) & ~MUX_PAD_CTRL_MASK)
> +		| MUX_PAD_CTRL(WEAK_PULLDOWN),
> +	(MX6PAD(NANDF_CS2__GPIO_6_15) & ~MUX_PAD_CTRL_MASK)
> +		| MUX_PAD_CTRL(OUTPUT_40OHM),
> +	(MX6PAD(NANDF_CS3__GPIO_6_16) & ~MUX_PAD_CTRL_MASK)
> +		| MUX_PAD_CTRL(OUTPUT_40OHM),
> +};
> +#define WL12XX_WL_IRQ_GP	IMX_GPIO_NR(6, 14)
> +#define WL12XX_WL_ENABLE_GP	IMX_GPIO_NR(6, 15)
> +#define WL12XX_BT_ENABLE_GP	IMX_GPIO_NR(6, 16)
> +
> +/* Button assignments for J14 */
> +static iomux_v3_cfg_t const button_pads[] = {
> +	/* Menu */
> +	MX6PAD(NANDF_D1__GPIO_2_1)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +	/* Back */
> +	MX6PAD(NANDF_D2__GPIO_2_2)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +	/* Labelled Search (mapped to Power under Android) */
> +	MX6PAD(NANDF_D3__GPIO_2_3)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +	/* Home */
> +	MX6PAD(NANDF_D4__GPIO_2_4)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +	/* Volume Down */
> +	MX6PAD(GPIO_19__GPIO_4_5)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +	/* Volume Up */
> +	MX6PAD(GPIO_18__GPIO_7_13)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> +	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
> +	gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
> +	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
> +	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
> +	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
> +
> +	/* Need delay 10ms according to KSZ9021 spec */
> +	udelay(1000 * 10);
> +	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
> +	gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
> +
> +	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
> +}
> +
> +iomux_v3_cfg_t const usb_pads[] = {
> +	MX6PAD(GPIO_17__GPIO_7_12) | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static void setup_iomux_uart(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> +	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX6
> +int board_ehci_hcd_init(int port)
> +{
> +	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
> +
> +	/* Reset USB hub */
> +	gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
> +	mdelay(2);
> +	gpio_set_value(IMX_GPIO_NR(7, 12), 1);
> +
> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg usdhc_cfg[2] = {
> +	{USDHC3_BASE_ADDR},
> +	{USDHC4_BASE_ADDR},
> +};
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret;
> +
> +	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
> +		gpio_direction_input(IMX_GPIO_NR(7, 0));
> +		ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
> +	} else {
> +		gpio_direction_input(IMX_GPIO_NR(2, 6));
> +		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
> +	}
> +
> +	return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> +	s32 status = 0;
> +	u32 index = 0;
> +
> +	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> +
> +	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
> +		switch (index) {
> +		case 0:
> +			imx_iomux_v3_setup_multiple_pads(
> +				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> +			break;
> +		case 1:
> +		       imx_iomux_v3_setup_multiple_pads(
> +			       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
> +		       break;
> +		default:
> +		       printf("Warning: you configured more USDHC controllers"
> +			       "(%d) then supported by the board (%d)\n",
> +			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
> +		       return status;
> +		}
> +
> +		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
> +	}
> +
> +	return status;
> +}
> +#endif
> +
> +u32 get_board_rev(void)
> +{
> +	return 0x63000;
> +}
> +
> +#ifdef CONFIG_MXC_SPI
> +iomux_v3_cfg_t const ecspi1_pads[] = {
> +	/* SS1 */
> +	MX6PAD(EIM_D19__GPIO_3_19)   | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6PAD(EIM_D17__ECSPI1_MISO) | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6PAD(EIM_D18__ECSPI1_MOSI) | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +	MX6PAD(EIM_D16__ECSPI1_SCLK) | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +};
> +
> +void setup_spi(void)
> +{
> +	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
> +	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
> +					 ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	/* min rx data delay */
> +	ksz9021_phy_extended_write(phydev,
> +			MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
> +	/* min tx data delay */
> +	ksz9021_phy_extended_write(phydev,
> +			MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
> +	/* max rx/tx clock delay, min rx/tx control */
> +	ksz9021_phy_extended_write(phydev,
> +			MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
> +	if (phydev->drv->config)
> +		phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +	int ret;
> +
> +	setup_iomux_enet();
> +
> +	ret = cpu_eth_init(bis);
> +	if (ret)
> +		printf("FEC MXC: %s:failed\n", __func__);
> +
> +	return 0;
> +}
> +
> +static void setup_buttons(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(button_pads,
> +					 ARRAY_SIZE(button_pads));
> +}
> +
> +#ifdef CONFIG_CMD_SATA
> +
> +int setup_sata(void)
> +{
> +	struct iomuxc_base_regs *const iomuxc_regs
> +		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
> +	int ret = enable_sata_clock();
> +	if (ret)
> +		return ret;
> +
> +	clrsetbits_le32(&iomuxc_regs->gpr[13],
> +			IOMUXC_GPR13_SATA_MASK,
> +			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
> +			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
> +			|IOMUXC_GPR13_SATA_SPEED_3G
> +			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
> +			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
> +			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
> +			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
> +			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
> +			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
> +
> +	return 0;
> +}
> +#endif
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +
> +static iomux_v3_cfg_t const backlight_pads[] = {
> +	/* Backlight on RGB connector: J15 */
> +	MX6PAD(SD1_DAT3__GPIO_1_21) | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
> +
> +	/* Backlight on LVDS connector: J6 */
> +	MX6PAD(SD1_CMD__GPIO_1_18) | MUX_PAD_CTRL(NO_PAD_CTRL),
> +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
> +};
> +
> +static iomux_v3_cfg_t const rgb_pads[] = {
> +	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
> +	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),
> +	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),
> +	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),
> +	MX6PAD(DI0_PIN4__GPIO_4_20),
> +	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
> +	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
> +	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
> +	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
> +	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
> +	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
> +	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
> +	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
> +	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
> +	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
> +	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
> +	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
> +	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
> +	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
> +	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
> +	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
> +	MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16),
> +	MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17),
> +	MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18),
> +	MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19),
> +	MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20),
> +	MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21),
> +	MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22),
> +	MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23),
> +};
> +
> +struct display_info_t {
> +	int	bus;
> +	int	addr;
> +	int	pixfmt;
> +	int	(*detect)(struct display_info_t const *dev);
> +	void	(*enable)(struct display_info_t const *dev);
> +	struct	fb_videomode mode;
> +};
> +
> +
> +static int detect_hdmi(struct display_info_t const *dev)
> +{
> +	return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
> +}
> +
> +static void enable_hdmi(struct display_info_t const *dev)
> +{
> +	u8 reg;
> +	printf("%s: setup HDMI monitor\n", __func__);
> +	reg = __raw_readb(
> +			HDMI_ARB_BASE_ADDR
> +			+HDMI_PHY_CONF0);
> +	reg |= HDMI_PHY_CONF0_PDZ_MASK;
> +	__raw_writeb(reg,
> +		     HDMI_ARB_BASE_ADDR
> +			+HDMI_PHY_CONF0);
> +	udelay(3000);
> +	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> +	__raw_writeb(reg,
> +		     HDMI_ARB_BASE_ADDR
> +			+HDMI_PHY_CONF0);
> +	udelay(3000);
> +	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> +	__raw_writeb(reg,
> +		     HDMI_ARB_BASE_ADDR
> +			+HDMI_PHY_CONF0);
> +	__raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
> +		     HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
> +}
> +
> +static int detect_i2c(struct display_info_t const *dev)
> +{
> +	return ((0 == i2c_set_bus_num(dev->bus))
> +		&&
> +		(0 == i2c_probe(dev->addr)));
> +}
> +
> +static void enable_lvds(struct display_info_t const *dev)
> +{
> +	struct iomuxc *iomux = (struct iomuxc *)
> +				IOMUXC_BASE_ADDR;
> +	u32 reg = readl(&iomux->gpr[2]);
> +	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
> +	writel(reg, &iomux->gpr[2]);
> +	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
> +}
> +
> +static void enable_rgb(struct display_info_t const *dev)
> +{
> +	imx_iomux_v3_setup_multiple_pads(
> +		rgb_pads,
> +		 ARRAY_SIZE(rgb_pads));
> +	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
> +}
> +
> +static struct display_info_t const displays[] = {{
> +	.bus	= -1,
> +	.addr	= 0,
> +	.pixfmt	= IPU_PIX_FMT_RGB24,
> +	.detect	= detect_hdmi,
> +	.enable	= enable_hdmi,
> +	.mode	= {
> +		.name           = "HDMI",
> +		.refresh        = 60,
> +		.xres           = 1024,
> +		.yres           = 768,
> +		.pixclock       = 15385,
> +		.left_margin    = 220,
> +		.right_margin   = 40,
> +		.upper_margin   = 21,
> +		.lower_margin   = 7,
> +		.hsync_len      = 60,
> +		.vsync_len      = 10,
> +		.sync           = FB_SYNC_EXT,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} }, {
> +	.bus	= 2,
> +	.addr	= 0x4,
> +	.pixfmt	= IPU_PIX_FMT_LVDS666,
> +	.detect	= detect_i2c,
> +	.enable	= enable_lvds,
> +	.mode	= {
> +		.name           = "Hannstar-XGA",
> +		.refresh        = 60,
> +		.xres           = 1024,
> +		.yres           = 768,
> +		.pixclock       = 15385,
> +		.left_margin    = 220,
> +		.right_margin   = 40,
> +		.upper_margin   = 21,
> +		.lower_margin   = 7,
> +		.hsync_len      = 60,
> +		.vsync_len      = 10,
> +		.sync           = FB_SYNC_EXT,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} }, {
> +	.bus	= 2,
> +	.addr	= 0x38,
> +	.pixfmt	= IPU_PIX_FMT_LVDS666,
> +	.detect	= detect_i2c,
> +	.enable	= enable_lvds,
> +	.mode	= {
> +		.name           = "wsvga-lvds",
> +		.refresh        = 60,
> +		.xres           = 1024,
> +		.yres           = 600,
> +		.pixclock       = 15385,
> +		.left_margin    = 220,
> +		.right_margin   = 40,
> +		.upper_margin   = 21,
> +		.lower_margin   = 7,
> +		.hsync_len      = 60,
> +		.vsync_len      = 10,
> +		.sync           = FB_SYNC_EXT,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} }, {
> +	.bus	= 2,
> +	.addr	= 0x48,
> +	.pixfmt	= IPU_PIX_FMT_RGB666,
> +	.detect	= detect_i2c,
> +	.enable	= enable_rgb,
> +	.mode	= {
> +		.name           = "wvga-rgb",
> +		.refresh        = 57,
> +		.xres           = 800,
> +		.yres           = 480,
> +		.pixclock       = 37037,
> +		.left_margin    = 40,
> +		.right_margin   = 60,
> +		.upper_margin   = 10,
> +		.lower_margin   = 10,
> +		.hsync_len      = 20,
> +		.vsync_len      = 10,
> +		.sync           = 0,
> +		.vmode          = FB_VMODE_NONINTERLACED
> +} } };
> +
> +int board_video_skip(void)
> +{
> +	int i;
> +	int ret;
> +	char const *panel = getenv("panel");
> +	if (!panel) {
> +		for (i = 0; i < ARRAY_SIZE(displays); i++) {
> +			struct display_info_t const *dev = displays+i;
> +			if (dev->detect(dev)) {
> +				panel = dev->mode.name;
> +				printf("auto-detected panel %s\n", panel);
> +				break;
> +			}
> +		}
> +		if (!panel) {
> +			panel = displays[0].mode.name;
> +			printf("No panel detected: default to %s\n", panel);
> +		}
> +	} else {
> +		for (i = 0; i < ARRAY_SIZE(displays); i++) {
> +			if (!strcmp(panel, displays[i].mode.name))
> +				break;
> +		}
> +	}
> +	if (i < ARRAY_SIZE(displays)) {
> +		ret = ipuv3_fb_init(&displays[i].mode, 0,
> +				    displays[i].pixfmt);
> +		if (!ret) {
> +			displays[i].enable(displays+i);
> +			printf("Display: %s (%ux%u)\n",
> +			       displays[i].mode.name,
> +			       displays[i].mode.xres,
> +			       displays[i].mode.yres);
> +		} else
> +			printf("LCD %s cannot be configured: %d\n",
> +			       displays[i].mode.name, ret);
> +	} else {
> +		printf("unsupported panel %s\n", panel);
> +		ret = -EINVAL;
> +	}
> +	return (0 != ret);
> +}
> +
> +static void setup_display(void)
> +{
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
> +	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> +	int reg;
> +
> +	/* Turn on LDB0,IPU,IPU DI0 clocks */
> +	reg = __raw_readl(&mxc_ccm->CCGR3);
> +	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
> +		|MXC_CCM_CCGR3_LDB_DI0_MASK;
> +	writel(reg, &mxc_ccm->CCGR3);
> +
> +	/* Turn on HDMI PHY clock */
> +	reg = __raw_readl(&mxc_ccm->CCGR2);
> +	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
> +	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> +	writel(reg, &mxc_ccm->CCGR2);
> +
> +	/* clear HDMI PHY reset */
> +	__raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
> +		     HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
> +
> +	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
> +	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
> +	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
> +
> +	/* set LDB0, LDB1 clk select to 011/011 */
> +	reg = readl(&mxc_ccm->cs2cdr);
> +	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
> +		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
> +	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
> +	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
> +	writel(reg, &mxc_ccm->cs2cdr);
> +
> +	reg = readl(&mxc_ccm->cscmr2);
> +	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
> +	writel(reg, &mxc_ccm->cscmr2);
> +
> +	reg = readl(&mxc_ccm->chsccdr);
> +	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
> +		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
> +		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
> +	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> +		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
> +	      |(CHSCCDR_PODF_DIVIDE_BY_3
> +		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> +	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
> +		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> +	writel(reg, &mxc_ccm->chsccdr);
> +
> +	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
> +	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
> +	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
> +	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
> +	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
> +	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
> +	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
> +	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
> +	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
> +	writel(reg, &iomux->gpr[2]);
> +
> +	reg = readl(&iomux->gpr[3]);
> +	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
> +	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
> +	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
> +	writel(reg, &iomux->gpr[3]);
> +
> +	/* backlights off until needed */
> +	imx_iomux_v3_setup_multiple_pads(backlight_pads,
> +					 ARRAY_SIZE(backlight_pads));
> +	gpio_direction_input(LVDS_BACKLIGHT_GP);
> +	gpio_direction_input(RGB_BACKLIGHT_GP);
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> +	setup_iomux_uart();
> +
> +	/* Disable wl1271 For Nitrogen6w */
> +	gpio_direction_input(WL12XX_WL_IRQ_GP);
> +	gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
> +	gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
> +
> +	imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
> +	setup_buttons();
> +
> +#if defined(CONFIG_VIDEO_IPUV3)
> +	setup_display();
> +#endif
> +	return 0;
> +}
> +
> +/*
> + * Do not overwrite the console
> + * Use always serial for U-Boot console
> + */
> +int overwrite_console(void)
> +{
> +	return 1;
> +}
> +
> +int board_init(void)
> +{
> +	/* address of boot parameters */
> +	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> +#ifdef CONFIG_MXC_SPI
> +	setup_spi();
> +#endif
> +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
> +	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> +
> +#ifdef CONFIG_CMD_SATA
> +	setup_sata();
> +#endif
> +
> +	return 0;
> +}
> +
> +int checkboard(void)
> +{
> +	if (gpio_get_value(WL12XX_WL_IRQ_GP))
> +		puts("Board: Nitrogen6X\n");
> +	else
> +		puts("Board: SABRE Lite\n");
> +
> +	return 0;
> +}
> +
> +struct button_key {
> +	char const	*name;
> +	unsigned	gpnum;
> +	char		ident;
> +};
> +
> +static struct button_key const buttons[] = {
> +	{"back",	IMX_GPIO_NR(2, 2),	'B'},
> +	{"home",	IMX_GPIO_NR(2, 4),	'H'},
> +	{"menu",	IMX_GPIO_NR(2, 1),	'M'},
> +	{"search",	IMX_GPIO_NR(2, 3),	'S'},
> +	{"volup",	IMX_GPIO_NR(7, 13),	'V'},
> +	{"voldown",	IMX_GPIO_NR(4, 5),	'v'},
> +};
> +
> +/*
> + * generate a null-terminated string containing the buttons pressed
> + * returns number of keys pressed
> + */
> +static int read_keys(char *buf)
> +{
> +	int i, numpressed = 0;
> +	for (i = 0; i < ARRAY_SIZE(buttons); i++) {
> +		if (!gpio_get_value(buttons[i].gpnum))
> +			buf[numpressed++] = buttons[i].ident;
> +	}
> +	buf[numpressed] = '\0';
> +	return numpressed;
> +}
> +
> +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	char envvalue[ARRAY_SIZE(buttons)+1];
> +	int numpressed = read_keys(envvalue);
> +	setenv("keybd", envvalue);
> +	return numpressed == 0;
> +}
> +
> +U_BOOT_CMD(
> +	kbd, 1, 1, do_kbd,
> +	"Tests for keypresses, sets 'keybd' environment variable",
> +	"Returns 0 (true) to shell if key is pressed."
> +);
> +
> +#ifdef CONFIG_PREBOOT
> +static char const kbd_magic_prefix[] = "key_magic";
> +static char const kbd_command_prefix[] = "key_cmd";
> +
> +static void preboot_keys(void)
> +{
> +	int numpressed;
> +	char keypress[ARRAY_SIZE(buttons)+1];
> +	numpressed = read_keys(keypress);
> +	if (numpressed) {
> +		char *kbd_magic_keys = getenv("magic_keys");
> +		char *suffix;
> +		/*
> +		 * loop over all magic keys
> +		 */
> +		for (suffix = kbd_magic_keys; *suffix; ++suffix) {
> +			char *keys;
> +			char magic[sizeof(kbd_magic_prefix) + 1];
> +			sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
> +			keys = getenv(magic);
> +			if (keys) {
> +				if (!strcmp(keys, keypress))
> +					break;
> +			}
> +		}
> +		if (*suffix) {
> +			char cmd_name[sizeof(kbd_command_prefix) + 1];
> +			char *cmd;
> +			sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
> +			cmd = getenv(cmd_name);
> +			if (cmd) {
> +				setenv("preboot", cmd);
> +				return;
> +			}
> +		}
> +	}
> +}
> +#endif
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> +	/* 4 bit bus width */
> +	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
> +	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
> +	{NULL,		0},
> +};
> +#endif
> +
> +int misc_init_r(void)
> +{
> +#ifdef CONFIG_PREBOOT
> +	preboot_keys();
> +#endif
> +
> +#ifdef CONFIG_CMD_BMODE
> +	add_board_boot_modes(board_boot_modes);
> +#endif
> +	return 0;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index 7d03620..d778f63 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -252,6 +252,12 @@ mx6qarm2                     arm         armv7       mx6qarm2            freesca
>  mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
>  mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
>  mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
> +nitrogen6q                   arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q
> +nitrogen6dl                  arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
> +nitrogen6s                   arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S
> +nitrogen6q2g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q
> +nitrogen6dl2g                arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL
> +nitrogen6s1g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S
>  eco5pk                       arm         armv7       eco5pk              8dtech         omap3
>  cm_t35                       arm         armv7       cm_t35              -              omap3
>  omap3_overo                  arm         armv7       overo               -              omap3
> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
> index 1b20e41..c1ae3d9 100644
> --- a/drivers/usb/host/ehci-mx6.c
> +++ b/drivers/usb/host/ehci-mx6.c
> @@ -21,7 +21,6 @@
>  #include <asm/io.h>
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/clock.h>
> -#include <asm/arch/mx6x_pins.h>
>  #include <asm/imx-common/iomux-v3.h>

Move this to a separate patch, as it is for all MX6. Add USB maintainer
to the list (Marek Vasut), even if it is a small change.

>  
>  #include "ehci.h"
> diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
> new file mode 100644
> index 0000000..ef6089a
> --- /dev/null
> +++ b/include/configs/nitrogen6x.h
> @@ -0,0 +1,284 @@
> +/*
> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Boundary Devices Nitrogen6X
> + * and Freescale i.MX6Q Sabre Lite boards.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_MX6
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_MACH_TYPE	3769
> +
> +#include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_MISC_INIT_R
> +#define CONFIG_MXC_GPIO
> +
> +#define CONFIG_MXC_UART
> +#define CONFIG_MXC_UART_BASE	       UART2_BASE
> +
> +#define CONFIG_CMD_SF
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_SST
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS  0
> +#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
> +#define CONFIG_SF_DEFAULT_SPEED 25000000
> +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
> +#endif
> +
> +/* I2C Configs */
> +#define CONFIG_CMD_I2C
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_I2C_MXC
> +#define CONFIG_SYS_I2C_SPEED		100000
> +
> +/* OCOTP Configs */
> +#define CONFIG_CMD_IMXOTP
> +#ifdef CONFIG_CMD_IMXOTP
> +#define CONFIG_IMX_OTP
> +#define IMX_OTP_BASE			OCOTP_BASE_ADDR
> +#define IMX_OTP_ADDR_MAX		0x7F
> +#define IMX_OTP_DATA_ERROR_VAL		0xBADABADA
> +/* #define IMX_OTPWRITE_ENABLED */
> +#endif
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR      0
> +#define CONFIG_SYS_FSL_USDHC_NUM       2
> +
> +#define CONFIG_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +
> +#ifdef CONFIG_MX6Q
> +#define CONFIG_CMD_SATA
> +#endif
> +
> +/*
> + * SATA Configs
> + */
> +#ifdef CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE	1
> +#define CONFIG_DWC_AHSATA_PORT_ID	0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +#endif
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE			ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE		RGMII
> +#define CONFIG_ETHPRIME			"FEC"
> +#define CONFIG_FEC_MXC_PHYADDR		6
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +#define CONFIG_PHY_MICREL_KSZ9021
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#define CONFIG_CMD_FAT
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX6
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_USB_ETHER_SMSC95XX
> +#define CONFIG_MXC_USB_PORT	1
> +#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS	0
> +
> +/* Miscellaneous commands */
> +#define CONFIG_CMD_BMODE
> +#define CONFIG_CMD_SETEXPR
> +
> +/* Framebuffer and LCD */
> +#define CONFIG_VIDEO
> +#define CONFIG_VIDEO_IPUV3
> +#define CONFIG_CFB_CONSOLE
> +#define CONFIG_VGA_AS_SINGLE_DEVICE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
> +#define CONFIG_VIDEO_BMP_RLE8
> +#define CONFIG_SPLASH_SCREEN
> +#define CONFIG_BMP_16BPP
> +#define CONFIG_VIDEO_LOGO
> +#define CONFIG_IPUV3_CLK 260000000
> +#define CONFIG_CMD_HDMIDETECT
> +#define CONFIG_CONSOLE_MUX
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX	       1
> +#define CONFIG_BAUDRATE			       115200
> +
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY	       1
> +
> +#define CONFIG_PREBOOT                 ""
> +
> +#define CONFIG_LOADADDR			       0x12000000
> +#define CONFIG_SYS_TEXT_BASE	       0x17800000
> +
> +#ifdef CONFIG_CMD_SATA
> +#define CONFIG_DRIVE_SATA "sata "
> +#else
> +#define CONFIG_DRIVE_SATA
> +#endif
> +
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_DRIVE_MMC "mmc "
> +#else
> +#define CONFIG_DRIVE_MMC
> +#endif
> +
> +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"console=ttymxc1\0" \
> +	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
> +		"sf erase 0xc0000 0x2000 && " \
> +		"echo restored environment to factory default ; fi\0" \
> +	"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
> +		"; do " \
> +			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
> +				"for fs in fat ext2 ; do " \
> +					"${fs}load " \
> +						"${dtype} ${disk}:1 " \
> +						"10008000 " \
> +						"/6x_bootscript" \
> +						"&& source 10008000 ; " \
> +				"done ; " \
> +			"done ; " \
> +		"done; " \
> +		"setenv stdout serial,vga ; " \
> +		"echo ; echo 6x_bootscript not found ; " \
> +		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
> +		"echo details at http://boundarydevices.com/6q_bootscript ; " \
> +		"setenv stdout serial\0" \
> +	"upgradeu=for dtype in sata mmc " CONFIG_DRIVE_TYPES \
> +		"; do " \
> +		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
> +		     "for fs in fat ext2 ; do " \
> +				"${fs}load ${dtype} ${disk}:1 10008000 " \
> +					"/6x_upgrade " \
> +					"&& source 10008000 ; " \
> +			"done ; " \
> +		"done ; " \
> +	"done\0" \
> +
> +#define CONFIG_ARP_TIMEOUT     200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT	       "U-Boot > "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE	       1024
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS	       16
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START       0x10000000
> +#define CONFIG_SYS_MEMTEST_END	       0x10010000
> +
> +#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ		       1000
> +
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS	       1
> +#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
> +#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE			(8 * 1024)
> +
> +/* #define CONFIG_ENV_IS_IN_MMC */
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV		0
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +#define CONFIG_ENV_OFFSET		(768 * 1024)
> +#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
> +#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
> +#endif
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +#define CONFIG_CMD_BMP
> +
> +#endif	       /* __CONFIG_H */
>
Eric Nelson - Feb. 14, 2013, 3:54 a.m.
Thanks for the review, Stefano.

On 02/12/2013 02:12 AM, Stefano Babic wrote:
> On 30/01/2013 19:10, Eric Nelson wrote:
>> This patch adds support for the Nitrogen6X board(s) from
>> Boundary Devices. The boards are based on the i.MX6x
>> processor family with two major variants:	
>> 	i.MX6Quad/6Dual
>> 	i.MX6Dual-Lite/6Solo
>>
>> More specifically, the board variations are:
>>         nitrogen6q              i.MX6Q/6D       1GB
>>         nitrogen6dl             i.MX6DL         1GB
>>         nitrogen6s              i.MX6S          512MB
>>         nitrogen6q2g            i.MX6Q/6D       2GB
>>         nitrogen6dl2g           i.MX6DL         2GB
>>         nitrogen6s1g            i.MX6S          1GB
>>
>> Refer to http://boundarydevices.com/products/ for details.
>
> Hi Eric,
>
> some general comments in praparation your V2. I have only some minor points.
>
> - Try to split your patch in several patches, if possible. The patch
> covers different issues and the series will be easy to be review. This
> is mainly for the changes outside boards/boundary - I know it is not
> easy to split the rest.
>
Understood. I submitted this as one big patch to show things
in context.

> - I agree you put your script in the board directory instead opf trying
> to use CONFIG_EXTRA_ENV_SETTINGS.
>
Cool.

> - Agree with the split of the configuration data (clocks.cfg and ddr
> setup). The same mechanism can be reused for other boards, too.
>

Thanks. Note that there's a bit of hand-waving for things that
don't quite fit, but the essential differences in memory setup
are properly partitioned.

> - and agree with the nomenclature. My +1 to rename mx6x_pins.h to
> mx6q_pins.h as you suggest in the cover letter.
>
Will do. I'll submit that before V2 of Nitrogen6X support so
it can be discussed separately.

Regards,


Eric
Fabio Estevam - March 8, 2013, 10:49 p.m.
Hi Eric,

On Wed, Jan 30, 2013 at 4:10 PM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> This patch adds support for the Nitrogen6X board(s) from
> Boundary Devices. The boards are based on the i.MX6x
> processor family with two major variants:
>         i.MX6Quad/6Dual
>         i.MX6Dual-Lite/6Solo
....
>  board/boundary/nitrogen6x/800mhz_2x128mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_2x256mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_4x128mx16.cfg     |   37 +
>  board/boundary/nitrogen6x/800mhz_4x256mx16.cfg     |   37 +

Good work, I really like this series.

I managed to test it and added support for a mx6dl board.

I would like to suggest if you could move the different memory inits
(like 800mhz_4x256mx16.cfg) into a common directory so that other
boards can pull their DDR init from there when possible.

Do you think we still can make this go into 2013.04?

Thanks,

Fabio Estevam
Eric Nelson - March 8, 2013, 11:25 p.m.
Thanks for the review Fabio,

On 03/08/2013 03:49 PM, Fabio Estevam wrote:
> Hi Eric,
>
> On Wed, Jan 30, 2013 at 4:10 PM, Eric Nelson
> <eric.nelson@boundarydevices.com> wrote:
>> This patch adds support for the Nitrogen6X board(s) from
>> Boundary Devices. The boards are based on the i.MX6x
>> processor family with two major variants:
>>          i.MX6Quad/6Dual
>>          i.MX6Dual-Lite/6Solo
> ....
>>   board/boundary/nitrogen6x/800mhz_2x128mx16.cfg     |   37 +
>>   board/boundary/nitrogen6x/800mhz_2x256mx16.cfg     |   37 +
>>   board/boundary/nitrogen6x/800mhz_4x128mx16.cfg     |   37 +
>>   board/boundary/nitrogen6x/800mhz_4x256mx16.cfg     |   37 +
>
> Good work, I really like this series.
>

Glad to hear it.

> I managed to test it and added support for a mx6dl board.
>
> I would like to suggest if you could move the different memory inits
> (like 800mhz_4x256mx16.cfg) into a common directory so that other
> boards can pull their DDR init from there when possible.
>

Okay, but this might be a bit of a stretch. We went through a
lot of our SABRE Lite, Nitrogen6x, and Nitrogen6x SOM boards
to select the right median values for the termination values
and such.

These may not apply for other boards, so another level of
indirection might be appropriate.

IOW, while most of the registers in the files like
800mhz_4x256mx16.cfg are for the memory **arrangement**,
some of them are or could be specific to the layout and
PCB fabrication details.

> Do you think we still can make this go into 2013.04?
>
Yep.

Now that this guy at Freescale fixed up the HDMI stuff,
I can even re-send the HDMI detect patch ;)

I'll send V2 tomorrow.

Regards,


Eric

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index faa9b5e..720beab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1029,6 +1029,14 @@  Pali Rohár <pali.rohar@gmail.com>
 
 	nokia_rx51	ARM ARMV7 (OMAP34xx SoC)
 
+Eric Nelson <eric.nelson@boundarydevices.com>
+	nitrogen6q		i.MX6Q/6D	1GB
+	nitrogen6dl		i.MX6DL		1GB
+	nitrogen6s		i.MX6S		512MB
+	nitrogen6q2g    	i.MX6Q/6D	2GB
+	nitrogen6dl2g		i.MX6DL		2GB
+	nitrogen6s1g		i.MX6S		1GB
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index d670f30..7676457 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,6 +20,17 @@ 
 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 
+#define CCM_CCGR0		0x020C4068
+#define CCM_CCGR1		0x020C406c
+#define CCM_CCGR2		0x020C4070
+#define CCM_CCGR3		0x020C4074
+#define CCM_CCGR4		0x020C4078
+#define CCM_CCGR5		0x020C407c
+#define CCM_CCGR6		0x020C4080
+
+#define PMU_MISC2		0x020C8170
+
+#ifndef __ASSEMBLY__
 struct mxc_ccm_reg {
 	u32 ccr;	/* 0x0000 */
 	u32 ccdr;
@@ -105,6 +116,7 @@  struct mxc_ccm_reg {
 	u32 analog_pfd_528_clr;
 	u32 analog_pfd_528_tog;
 };
+#endif
 
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_RBC_EN				(1 << 27)
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index d23abd7..57b514f 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -16,6 +16,11 @@ 
 
 #ifndef __ASM_ARCH_IOMUX_H__
 #define __ASM_ARCH_IOMUX_H__
+
+#define IOMUXC_GPR4		0x020e0010
+#define IOMUXC_GPR6		0x020e0018
+#define IOMUXC_GPR7		0x020e001c
+
 /*
  * IOMUXC_GPR13 bit fields
  */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
new file mode 100644
index 0000000..0a3cddc
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -0,0 +1,73 @@ 
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_MX6_DDR_H__
+#define __ASM_ARCH_MX6_DDR_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q-ddr.h"
+#else
+#ifdef CONFIG_MX6DL
+#include "mx6dl-ddr.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6DL */
+#endif	/* CONFIG_MX6Q */
+
+#define MMDC_P0_MDCTL		0x021b0000
+#define MMDC_P0_MDPDC		0x021b0004
+#define MMDC_P0_MDOTC		0x021b0008
+#define MMDC_P0_MDCFG0		0x021b000c
+#define MMDC_P0_MDCFG1		0x021b0010
+#define MMDC_P0_MDCFG2		0x021b0014
+#define MMDC_P0_MDMISC		0x021b0018
+#define MMDC_P0_MDSCR		0x021b001c
+#define MMDC_P0_MDREF		0x021b0020
+#define MMDC_P0_MDRWD		0x021b002c
+#define MMDC_P0_MDOR		0x021b0030
+#define MMDC_P0_MDASP		0x021b0040
+#define MMDC_P0_MAPSR		0x021b0404
+#define MMDC_P0_MPZQHWCTRL	0x021b0800
+#define MMDC_P0_MPWLDECTRL0	0x021b080c
+#define MMDC_P0_MPWLDECTRL1	0x021b0810
+#define MMDC_P0_MPODTCTRL	0x021b0818
+#define MMDC_P0_MPRDDQBY0DL	0x021b081c
+#define MMDC_P0_MPRDDQBY1DL	0x021b0820
+#define MMDC_P0_MPRDDQBY2DL	0x021b0824
+#define MMDC_P0_MPRDDQBY3DL	0x021b0828
+#define MMDC_P0_MPDGCTRL0	0x021b083c
+#define MMDC_P0_MPDGCTRL1	0x021b0840
+#define MMDC_P0_MPRDDLCTL	0x021b0848
+#define MMDC_P0_MPWRDLCTL	0x021b0850
+#define MMDC_P0_MPMUR0		0x021b08b8
+
+#define MMDC_P1_MDCTL		0x021b4000
+#define MMDC_P1_MDPDC		0x021b4004
+#define MMDC_P1_MDOTC		0x021b4008
+#define MMDC_P1_MDCFG0		0x021b400c
+#define MMDC_P1_MDCFG1		0x021b4010
+#define MMDC_P1_MDCFG2		0x021b4014
+#define MMDC_P1_MDMISC		0x021b4018
+#define MMDC_P1_MDSCR		0x021b401c
+#define MMDC_P1_MDREF		0x021b4020
+#define MMDC_P1_MDRWD		0x021b402c
+#define MMDC_P1_MDOR		0x021b4030
+#define MMDC_P1_MDASP		0x021b4040
+#define MMDC_P1_MAPSR		0x021b4404
+#define MMDC_P1_MPZQHWCTRL	0x021b4800
+#define MMDC_P1_MPWLDECTRL0	0x021b480c
+#define MMDC_P1_MPWLDECTRL1	0x021b4810
+#define MMDC_P1_MPODTCTRL	0x021b4818
+#define MMDC_P1_MPRDDQBY0DL	0x021b481c
+#define MMDC_P1_MPRDDQBY1DL	0x021b4820
+#define MMDC_P1_MPRDDQBY2DL	0x021b4824
+#define MMDC_P1_MPRDDQBY3DL	0x021b4828
+#define MMDC_P1_MPDGCTRL0	0x021b483c
+#define MMDC_P1_MPDGCTRL1	0x021b4840
+#define MMDC_P1_MPRDDLCTL	0x021b4848
+#define MMDC_P1_MPWRDLCTL	0x021b4850
+#define MMDC_P1_MPMUR0		0x021b48b8
+
+#endif	/*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
new file mode 100644
index 0000000..5a4bfc6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -0,0 +1,59 @@ 
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
+#define __ASM_ARCH_MX6DLS_DDR_H__
+
+#ifndef CONFIG_MX6DL
+#ifndef CONFIG_MX6S
+#error "wrong CPU"
+#endif
+#endif
+
+#define IOM_DRAM_DQM0		0x020e0470
+#define IOM_DRAM_DQM1		0x020e0474
+#define IOM_DRAM_DQM2		0x020e0478
+#define IOM_DRAM_DQM3		0x020e047c
+#define IOM_DRAM_DQM4		0x020e0480
+#define IOM_DRAM_DQM5		0x020e0484
+#define IOM_DRAM_DQM6		0x020e0488
+#define IOM_DRAM_DQM7		0x020e048c
+
+#define IOM_DRAM_CAS		0x020e0464
+#define IOM_DRAM_RAS		0x020e0490
+#define IOM_DRAM_RESET		0x020e0494
+#define IOM_DRAM_SDCLK_0	0x020e04ac
+#define IOM_DRAM_SDCLK_1	0x020e04b0
+#define IOM_DRAM_SDBA2		0x020e04a0
+#define IOM_DRAM_SDCKE0		0x020e04a4
+#define IOM_DRAM_SDCKE1		0x020e04a8
+#define IOM_DRAM_SDODT0		0x020e04b4
+#define IOM_DRAM_SDODT1		0x020e04b8
+
+#define IOM_DRAM_SDQS0		0x020e04bc
+#define IOM_DRAM_SDQS1		0x020e04c0
+#define IOM_DRAM_SDQS2		0x020e04c4
+#define IOM_DRAM_SDQS3		0x020e04c8
+#define IOM_DRAM_SDQS4		0x020e04cc
+#define IOM_DRAM_SDQS5		0x020e04d0
+#define IOM_DRAM_SDQS6		0x020e04d4
+#define IOM_DRAM_SDQS7		0x020e04d8
+
+#define IOM_GRP_B0DS		0x020e0764
+#define IOM_GRP_B1DS		0x020e0770
+#define IOM_GRP_B2DS		0x020e0778
+#define IOM_GRP_B3DS		0x020e077c
+#define IOM_GRP_B4DS		0x020e0780
+#define IOM_GRP_B5DS		0x020e0784
+#define IOM_GRP_B6DS		0x020e078c
+#define IOM_GRP_B7DS		0x020e0748
+#define IOM_GRP_ADDDS		0x020e074c
+#define IOM_DDRMODE_CTL		0x020e0750
+#define IOM_GRP_DDRPKE		0x020e0754
+#define IOM_GRP_DDRMODE		0x020e0760
+#define IOM_GRP_CTLDS		0x020e076c
+#define IOM_GRP_DDR_TYPE	0x020e0774
+
+#endif	/*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 79e2c4f..9b9c571 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -105,6 +105,9 @@  enum {
 	MX6DL_PAD_KEY_COL3__GPIO_4_12		= IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
 	MX6DL_PAD_KEY_ROW3__I2C2_SDA		= IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
 	MX6DL_PAD_KEY_ROW3__GPIO_4_13		= IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_CS1__GPIO_6_14		= IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_CS2__GPIO_6_15		= IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
+	MX6DL_PAD_NANDF_CS3__GPIO_6_16		= IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
 	MX6DL_PAD_NANDF_D1__GPIO_2_1		= IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
 	MX6DL_PAD_NANDF_D2__GPIO_2_2		= IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
 	MX6DL_PAD_NANDF_D3__GPIO_2_3		= IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
new file mode 100644
index 0000000..4060600
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -0,0 +1,57 @@ 
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_ARCH_MX6Q_DDR_H__
+#define __ASM_ARCH_MX6Q_DDR_H__
+
+#ifndef CONFIG_MX6Q
+#error "wrong CPU"
+#endif
+
+#define IOM_DRAM_DQM0		0x020e05ac
+#define IOM_DRAM_DQM1		0x020e05b4
+#define IOM_DRAM_DQM2		0x020e0528
+#define IOM_DRAM_DQM3		0x020e0520
+#define IOM_DRAM_DQM4		0x020e0514
+#define IOM_DRAM_DQM5		0x020e0510
+#define IOM_DRAM_DQM6		0x020e05bc
+#define IOM_DRAM_DQM7		0x020e05c4
+
+#define IOM_DRAM_CAS		0x020e056c
+#define IOM_DRAM_RAS		0x020e0578
+#define IOM_DRAM_RESET		0x020e057c
+#define IOM_DRAM_SDCLK_0	0x020e0588
+#define IOM_DRAM_SDCLK_1	0x020e0594
+#define IOM_DRAM_SDBA2		0x020e058c
+#define IOM_DRAM_SDCKE0		0x020e0590
+#define IOM_DRAM_SDCKE1		0x020e0598
+#define IOM_DRAM_SDODT0		0x020e059c
+#define IOM_DRAM_SDODT1		0x020e05a0
+
+#define IOM_DRAM_SDQS0		0x020e05a8
+#define IOM_DRAM_SDQS1		0x020e05b0
+#define IOM_DRAM_SDQS2		0x020e0524
+#define IOM_DRAM_SDQS3		0x020e051c
+#define IOM_DRAM_SDQS4		0x020e0518
+#define IOM_DRAM_SDQS5		0x020e050c
+#define IOM_DRAM_SDQS6		0x020e05b8
+#define IOM_DRAM_SDQS7		0x020e05c0
+
+#define IOM_GRP_B0DS		0x020e0784
+#define IOM_GRP_B1DS		0x020e0788
+#define IOM_GRP_B2DS		0x020e0794
+#define IOM_GRP_B3DS		0x020e079c
+#define IOM_GRP_B4DS		0x020e07a0
+#define IOM_GRP_B5DS		0x020e07a4
+#define IOM_GRP_B6DS		0x020e07a8
+#define IOM_GRP_B7DS		0x020e0748
+#define IOM_GRP_ADDDS		0x020e074c
+#define IOM_DDRMODE_CTL		0x020e0750
+#define IOM_GRP_DDRPKE		0x020e0758
+#define IOM_GRP_DDRMODE		0x020e0774
+#define IOM_GRP_CTLDS		0x020e078c
+#define IOM_GRP_DDR_TYPE	0x020e0798
+
+#endif	/*__ASM_ARCH_MX6Q_DDR_H__ */
diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
new file mode 100644
index 0000000..63fb31d
--- /dev/null
+++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x00020036
+DATA 4, MMDC_P0_MDCFG0, 0x555A7975
+DATA 4, MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x09444040
+DATA 4, MMDC_P0_MDPDC, 0x00025576
+DATA 4, MMDC_P0_MDASP, 0x00000027
+DATA 4, MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MMDC_P0_MDSCR, 0x04088032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00428031
+DATA 4, MMDC_P0_MDSCR, 0x09408030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00005800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x434B0350
+DATA 4, MMDC_P0_MPDGCTRL1, 0x034C0359
+DATA 4, MMDC_P1_MPDGCTRL0, 0x434B0350
+DATA 4, MMDC_P1_MPDGCTRL1, 0x03650348
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4436383B
+DATA 4, MMDC_P1_MPRDDLCTL, 0x39393341
+DATA 4, MMDC_P0_MPWRDLCTL, 0x35373933
+DATA 4, MMDC_P1_MPWRDLCTL, 0x48254A36
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x00440044
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x00440044
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..68e70ad
--- /dev/null
+++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x00020036
+DATA 4, MMDC_P0_MDCFG0, 0x895A7975
+DATA 4, MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x09444040
+DATA 4, MMDC_P0_MDPDC, 0x00025576
+DATA 4, MMDC_P0_MDASP, 0x00000047
+DATA 4, MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MMDC_P0_MDSCR, 0x04008032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00428031
+DATA 4, MMDC_P0_MDSCR, 0x09408030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00007800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x43040319
+DATA 4, MMDC_P0_MPDGCTRL1, 0x03040279
+DATA 4, MMDC_P1_MPDGCTRL0, 0x43040321
+DATA 4, MMDC_P1_MPDGCTRL1, 0x03030251
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4d434248
+DATA 4, MMDC_P1_MPRDDLCTL, 0x42413c4d
+DATA 4, MMDC_P0_MPWRDLCTL, 0x34424543
+DATA 4, MMDC_P1_MPWRDLCTL, 0x49324933
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x001a0017
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x00170027
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x000a001f
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt
new file mode 100644
index 0000000..fe75976
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript.txt
@@ -0,0 +1,58 @@ 
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	setenv fbmem "fbmem=28M";
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+i2c dev 2
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbmem "fbmem=10M";
+	else
+		setenv fbmem ${fbmem},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M root=/dev/mmcblk0p1 rootwait consoleblank=0 ;
+${fs}load mmc ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; echo "Error loading kernel image"
+
diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt
new file mode 100644
index 0000000..7ade2e5
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt
@@ -0,0 +1,64 @@ 
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=28M";
+	else
+		setenv fbcon ${fbcon},28M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000; echo "Error loading kernel image"
+
diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
new file mode 100644
index 0000000..7ade2e5
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
@@ -0,0 +1,64 @@ 
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=10M";
+	else
+		setenv fbcon ${fbcon},10M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+	setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+	if test "0" -eq $nextcon; then
+		setenv fbcon "fbcon=28M";
+	else
+		setenv fbcon ${fbcon},28M
+	fi
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000; echo "Error loading kernel image"
+
diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
new file mode 100644
index 0000000..354d1a2
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -0,0 +1,46 @@ 
+setenv stdout serial,vga
+echo "check U-Boot" ;
+setenv offset 0x400
+if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
+      echo "read $filesize bytes from SD card" ;
+      if sf probe || sf probe || \
+	 sf probe 1 27000000 || sf probe 1 27000000 ; then
+	   echo "probed SPI ROM" ;
+           if sf read 0x12400000 $offset $filesize ; then
+               if cmp.b 0x12000000 0x12400000 $filesize ; then
+                   echo "------- U-Boot versions match" ;
+               else
+                   echo "Need U-Boot upgrade" ;
+                   echo "Program in 5 seconds" ;
+                   for n in 5 4 3 2 1 ; do
+                        echo $n ;
+                        sleep 1 ;
+                   done
+		   echo "erasing" ;
+                   sf erase 0 0x50000 ;
+		   # two steps to prevent bricking
+		   echo "programming" ;
+                   sf write 0x12000000 $offset $filesize ;
+		   echo "verifying" ;
+                   if sf read 0x12400000 $offset $filesize ; then
+                       if cmp.b 0x12000000 0x12400000 $filesize ; then
+                           while echo "---- U-Boot upgraded. reset" ; do
+				sleep 120
+			   done
+                       else
+                           echo "Read verification error" ;
+                       fi
+                   else
+                        echo "Error re-reading EEPROM" ;
+                   fi
+               fi
+           else
+               echo "Error reading boot loader from EEPROM" ;
+           fi
+      else
+           echo "Error initializing EEPROM" ;
+      fi ;
+else
+     echo "No U-Boot image found on SD card" ;
+fi
+
diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
new file mode 100644
index 0000000..ffd1078
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MMDC_P0_MDCFG0, 0x696D5323
+DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x00333030
+DATA 4, MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MMDC_P0_MDASP, 0x00000017
+DATA 4, MMDC_P0_MDCTL, 0x83190000
+DATA 4, MMDC_P0_MDSCR, 0x04008032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00048031
+DATA 4, MMDC_P0_MDSCR, 0x07208030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00005800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
new file mode 100644
index 0000000..35b38b7
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MMDC_P0_MDCFG0, 0x696D5323
+DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x00333030
+DATA 4, MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MMDC_P0_MDASP, 0x00000027
+DATA 4, MMDC_P0_MDCTL, 0x84190000
+DATA 4, MMDC_P0_MDSCR, 0x04008032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00048031
+DATA 4, MMDC_P0_MDSCR, 0x07208030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00007800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
new file mode 100644
index 0000000..76ae7e9
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MMDC_P0_MDCFG0, 0x696D5323
+DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x00333030
+DATA 4, MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MMDC_P0_MDASP, 0x00000027
+DATA 4, MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MMDC_P0_MDSCR, 0x04008032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00048031
+DATA 4, MMDC_P0_MDSCR, 0x07208030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00005800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
new file mode 100644
index 0000000..8de937c
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
@@ -0,0 +1,37 @@ 
+DATA 4, MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MMDC_P0_MDCFG0, 0x696D5323
+DATA 4, MMDC_P0_MDCFG1, 0xB66E8C63
+DATA 4, MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MMDC_P0_MDOTC, 0x00333030
+DATA 4, MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MMDC_P0_MDASP, 0x00000047
+DATA 4, MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MMDC_P0_MDSCR, 0x04008032
+DATA 4, MMDC_P0_MDSCR, 0x00008033
+DATA 4, MMDC_P0_MDSCR, 0x00048031
+DATA 4, MMDC_P0_MDSCR, 0x07208030
+DATA 4, MMDC_P0_MDSCR, 0x04008040
+DATA 4, MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MMDC_P0_MDREF, 0x00007800
+DATA 4, MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MMDC_P0_MDSCR, 0x00000000
+DATA 4, MMDC_P0_MAPSR, 0x00011006
+
diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
new file mode 100644
index 0000000..63da7d0
--- /dev/null
+++ b/board/boundary/nitrogen6x/Makefile
@@ -0,0 +1,41 @@ 
+#
+# Copyright (C) 2012, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2012 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := nitrogen6x.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README
new file mode 100644
index 0000000..330cb49
--- /dev/null
+++ b/board/boundary/nitrogen6x/README
@@ -0,0 +1,93 @@ 
+U-Boot for the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards
+
+This file contains information for the port of
+U-Boot to the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards.
+
+1. Boot source, boot from SPI NOR
+---------------------------------
+The configuration in this directory supports both the
+Nitrogen6X and Freescale SabreLite board, but in a
+different fashion from Freescale's implementation in
+board/freescale/mx6qsabrelite.
+
+In particular, this image supports booting from SPI NOR
+and saving the environment to SPI NOR.
+
+It does not support 'boot from SD' at offset 0x400
+except through the 'bmode' command.
+	http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
+
+2. Boots using 6x_bootscript on SATA or SD card
+-----------------------------------------------
+The default bootcmd for these boards is configured
+to look for and source a boot script named '6x_bootscript'
+in the root of the first partition of the following
+devices:
+
+	sata 0
+	mmc 0
+	mmc 1
+
+They're searched in the order listed above, trying both the
+ext2 and fat filesystems.
+
+2. Maintaining the SPI NOR
+--------------------------
+A couple of convenience commands
+
+	clearenv - clear environment to factory default
+	upgradeu - look and source a boot script named
+		'6x_upgrade' to upgrade the U-Boot version
+		in SPI NOR. The search is the same as for
+		6x_bootscript described above.
+
+3. Display support
+------------------
+U-Boot support for the following displays is configured by
+default:
+
+    HDMI           - 1024 x 768 for maximum compatibility
+    Hannstar-XGA   - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
+    wsvga-lvds     - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
+    wvga-rgb       - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
+
+Since the ipuv3_fb display driver currently supports only a single display,
+this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
+or the I2C touch controller of the LVDS and RGB displays in the priority
+listed above.
+
+Setting 'panel' environment variable to one of the names above will
+override auto-detection and force activation of the specified panel.
+
+4. Building
+------------
+
+To build U-Boot for one of the Nitrogen6x or SabreLite board:
+
+	make nitrogen6x_config
+	make u-boot.imx
+
+Note that 'nitrogen6x' is a placeholder. The complete list of supported
+board configurations is shown in tha MAINTAINERS file:
+	nitrogen6q		i.MX6Q/6D	1GB
+	nitrogen6dl		i.MX6DL		1GB
+	nitrogen6s		i.MX6S		512MB
+	nitrogen6q2g    	i.MX6Q/6D	2GB
+	nitrogen6dl2g		i.MX6DL		2GB
+	nitrogen6s1g		i.MX6S		1GB
+
+The -6q variants support either the i.MX6Quad or i.MX6Dual processors
+and are configured for a 64-bit memory bus at 1066 MHz.
+
+The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
+
+The -6s variants use a 32-bit memory bus at 800MHz.
+
+If you place the u-boot.imx into a single-partition SD card
+along with a binary version of the boot script 6x_upgrade.txt,
+you can program it using 'upgradeu':
+
+	U-Boot> run upgradeu
+
diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
new file mode 100644
index 0000000..5143b78
--- /dev/null
+++ b/board/boundary/nitrogen6x/clocks.cfg
@@ -0,0 +1,31 @@ 
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, IOMUXC_GPR6, 0x007F007F
+DATA 4, IOMUXC_GPR7, 0x007F007F
+
+/* Set LDO Ramp rates to fast */
+/* 64 clocks/0.266uS/25mV */
+/* == 32uS for 0.95->1.25V */
+DATA 4, PMU_MISC2, 0x00670f67
diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
new file mode 100644
index 0000000..b3f7ec4
--- /dev/null
+++ b/board/boundary/nitrogen6x/ddr-setup.cfg
@@ -0,0 +1,94 @@ 
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, IOM_DRAM_SDQS0, 0x00000030
+DATA 4, IOM_DRAM_SDQS1, 0x00000030
+DATA 4, IOM_DRAM_SDQS2, 0x00000030
+DATA 4, IOM_DRAM_SDQS3, 0x00000030
+DATA 4, IOM_DRAM_SDQS4, 0x00000030
+DATA 4, IOM_DRAM_SDQS5, 0x00000030
+DATA 4, IOM_DRAM_SDQS6, 0x00000030
+DATA 4, IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, IOM_GRP_B0DS, 0x00000030
+DATA 4, IOM_GRP_B1DS, 0x00000030
+DATA 4, IOM_GRP_B2DS, 0x00000030
+DATA 4, IOM_GRP_B3DS, 0x00000030
+DATA 4, IOM_GRP_B4DS, 0x00000030
+DATA 4, IOM_GRP_B5DS, 0x00000030
+DATA 4, IOM_GRP_B6DS, 0x00000030
+DATA 4, IOM_GRP_B7DS, 0x00000030
+DATA 4, IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, IOM_DRAM_DQM0, 0x00020030
+DATA 4, IOM_DRAM_DQM1, 0x00020030
+DATA 4, IOM_DRAM_DQM2, 0x00020030
+DATA 4, IOM_DRAM_DQM3, 0x00020030
+DATA 4, IOM_DRAM_DQM4, 0x00020030
+DATA 4, IOM_DRAM_DQM5, 0x00020030
+DATA 4, IOM_DRAM_DQM6, 0x00020030
+DATA 4, IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, IOM_DRAM_CAS, 0x00020030
+DATA 4, IOM_DRAM_RAS, 0x00020030
+DATA 4, IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, IOM_DRAM_RESET, 0x000e0030
+DATA 4, IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, IOM_DRAM_SDODT0, 0x00003030
+DATA 4, IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, IOM_GRP_DDRPKE, 0x00000000
+DATA 4, IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+DATA 4, MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR	con_req
+ */
+DATA 4, MMDC_P0_MDSCR, 0x00008000
+
+
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
new file mode 100644
index 0000000..60300c5
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x128mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
new file mode 100644
index 0000000..b62c73e
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x256mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
new file mode 100644
index 0000000..30353a5
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x128mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
new file mode 100644
index 0000000..8c1a74f
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
new file mode 100644
index 0000000..8a73a51
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x128mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
new file mode 100644
index 0000000..3659e1e
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -0,0 +1,46 @@ 
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x256mx16.cfg"
+#include "clocks.cfg"
+
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
new file mode 100644
index 0000000..9e3898a
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -0,0 +1,901 @@ 
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#ifdef CONFIG_MX6Q
+#include <asm/arch/mx6x_pins.h>
+#else
+#ifdef CONFIG_MX6DL
+#include <asm/arch/mx6dl_pins.h>
+#define FOR_DL_SOLO
+#else
+#ifdef CONFIG_MX6S
+#include <asm/arch/mx6dl_pins.h>
+#define FOR_DL_SOLO
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6S */
+#endif	/* CONFIG_MX6DL */
+#endif	/* CONFIG_MX6Q */
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef FOR_DL_SOLO
+#define MX6PAD(a) MX6DL_PAD_##a
+#else
+#define MX6PAD(a) MX6Q_PAD_##a
+#endif
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6PAD(SD3_DAT6__UART1_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6PAD(SD3_DAT7__UART1_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6PAD(EIM_D26__UART2_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6PAD(EIM_D27__UART2_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1, SGTL5000 */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode = MX6PAD(EIM_D21__I2C1_SCL) | PC,
+		.gpio_mode = MX6PAD(EIM_D21__GPIO_3_21) | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode = MX6PAD(EIM_D28__I2C1_SDA) | PC,
+		.gpio_mode = MX6PAD(EIM_D28__GPIO_3_28) | PC,
+		.gp = IMX_GPIO_NR(3, 28)
+	}
+};
+
+/* I2C2 Camera, MIPI */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6PAD(KEY_COL3__I2C2_SCL) | PC,
+		.gpio_mode = MX6PAD(KEY_COL3__GPIO_4_12) | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6PAD(KEY_ROW3__I2C2_SDA) | PC,
+		.gpio_mode = MX6PAD(KEY_ROW3__GPIO_4_13) | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+/* I2C3, J15 - RGB connector */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6PAD(GPIO_5__I2C3_SCL) | PC,
+		.gpio_mode = MX6PAD(GPIO_5__GPIO_1_5) | PC,
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6PAD(GPIO_16__I2C3_SDA) | PC,
+		.gpio_mode = MX6PAD(GPIO_16__GPIO_7_11) | PC,
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6PAD(SD3_CLK__USDHC3_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_CMD__USDHC3_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT0__USDHC3_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT1__USDHC3_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT2__USDHC3_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT3__USDHC3_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT5__GPIO_7_0)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6PAD(SD4_CLK__USDHC4_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_CMD__USDHC4_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT0__USDHC4_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT1__USDHC4_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT2__USDHC4_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT3__USDHC4_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(NANDF_D6__GPIO_2_6)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+	MX6PAD(ENET_MDIO__ENET_MDIO)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(ENET_MDC__ENET_MDC)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TXC__ENET_RGMII_TXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD0__ENET_RGMII_TD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD1__ENET_RGMII_TD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD2__ENET_RGMII_TD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD3__ENET_RGMII_TD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TX_CTL__RGMII_TX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(ENET_REF_CLK__ENET_TX_CLK)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	MX6PAD(RGMII_RXC__GPIO_6_30)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6PAD(RGMII_RD0__GPIO_6_25)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6PAD(RGMII_RD1__GPIO_6_27)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6PAD(RGMII_RD2__GPIO_6_28)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6PAD(RGMII_RD3__GPIO_6_29)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6PAD(RGMII_RX_CTL__GPIO_6_24)	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	MX6PAD(EIM_D23__GPIO_3_23)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6PAD(ENET_RXD0__GPIO_1_27)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+	MX6PAD(RGMII_RXC__ENET_RGMII_RXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD0__ENET_RGMII_RD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD1__ENET_RGMII_RD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD2__ENET_RGMII_RD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD3__ENET_RGMII_RD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RX_CTL__RGMII_RX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+/* wl1271 pads on nitrogen6x */
+iomux_v3_cfg_t const wl12xx_pads[] = {
+	(MX6PAD(NANDF_CS1__GPIO_6_14) & ~MUX_PAD_CTRL_MASK)
+		| MUX_PAD_CTRL(WEAK_PULLDOWN),
+	(MX6PAD(NANDF_CS2__GPIO_6_15) & ~MUX_PAD_CTRL_MASK)
+		| MUX_PAD_CTRL(OUTPUT_40OHM),
+	(MX6PAD(NANDF_CS3__GPIO_6_16) & ~MUX_PAD_CTRL_MASK)
+		| MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+#define WL12XX_WL_IRQ_GP	IMX_GPIO_NR(6, 14)
+#define WL12XX_WL_ENABLE_GP	IMX_GPIO_NR(6, 15)
+#define WL12XX_BT_ENABLE_GP	IMX_GPIO_NR(6, 16)
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t const button_pads[] = {
+	/* Menu */
+	MX6PAD(NANDF_D1__GPIO_2_1)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Back */
+	MX6PAD(NANDF_D2__GPIO_2_2)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Labelled Search (mapped to Power under Android) */
+	MX6PAD(NANDF_D3__GPIO_2_3)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Home */
+	MX6PAD(NANDF_D4__GPIO_2_4)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Down */
+	MX6PAD(GPIO_19__GPIO_4_5)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Up */
+	MX6PAD(GPIO_18__GPIO_7_13)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
+	gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+	/* Need delay 10ms according to KSZ9021 spec */
+	udelay(1000 * 10);
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
+	gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	MX6PAD(GPIO_17__GPIO_7_12) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+	/* Reset USB hub */
+	gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
+	mdelay(2);
+	gpio_set_value(IMX_GPIO_NR(7, 12), 1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
+	} else {
+		gpio_direction_input(IMX_GPIO_NR(2, 6));
+		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		case 1:
+		       imx_iomux_v3_setup_multiple_pads(
+			       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		       break;
+		default:
+		       printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+		       return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+	return 0x63000;
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS1 */
+	MX6PAD(EIM_D19__GPIO_3_19)   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D17__ECSPI1_MISO) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D18__ECSPI1_MOSI) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D16__ECSPI1_SCLK) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev,
+			MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	setup_iomux_enet();
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		printf("FEC MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+static void setup_buttons(void)
+{
+	imx_iomux_v3_setup_multiple_pads(button_pads,
+					 ARRAY_SIZE(button_pads));
+}
+
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight on RGB connector: J15 */
+	MX6PAD(SD1_DAT3__GPIO_1_21) | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
+
+	/* Backlight on LVDS connector: J6 */
+	MX6PAD(SD1_CMD__GPIO_1_18) | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),
+	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),
+	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),
+	MX6PAD(DI0_PIN4__GPIO_4_20),
+	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
+	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
+	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
+	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
+	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
+	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
+	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
+	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
+	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
+	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
+	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
+	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
+	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
+	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
+	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
+	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
+	MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16),
+	MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17),
+	MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18),
+	MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19),
+	MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20),
+	MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21),
+	MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22),
+	MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23),
+};
+
+struct display_info_t {
+	int	bus;
+	int	addr;
+	int	pixfmt;
+	int	(*detect)(struct display_info_t const *dev);
+	void	(*enable)(struct display_info_t const *dev);
+	struct	fb_videomode mode;
+};
+
+
+static int detect_hdmi(struct display_info_t const *dev)
+{
+	return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	u8 reg;
+	printf("%s: setup HDMI monitor\n", __func__);
+	reg = __raw_readb(
+			HDMI_ARB_BASE_ADDR
+			+HDMI_PHY_CONF0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	__raw_writeb(reg,
+		     HDMI_ARB_BASE_ADDR
+			+HDMI_PHY_CONF0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	__raw_writeb(reg,
+		     HDMI_ARB_BASE_ADDR
+			+HDMI_PHY_CONF0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	__raw_writeb(reg,
+		     HDMI_ARB_BASE_ADDR
+			+HDMI_PHY_CONF0);
+	__raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
+		     HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return ((0 == i2c_set_bus_num(dev->bus))
+		&&
+		(0 == i2c_probe(dev->addr)));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		 ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+static struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x4,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x38,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "wsvga-lvds",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 2,
+	.addr	= 0x48,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_i2c,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 57,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 37037,
+		.left_margin    = 40,
+		.right_margin   = 60,
+		.upper_margin   = 10,
+		.lower_margin   = 10,
+		.hsync_len      = 20,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+
+int board_video_skip(void)
+{
+	int i;
+	int ret;
+	char const *panel = getenv("panel");
+	if (!panel) {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			struct display_info_t const *dev = displays+i;
+			if (dev->detect(dev)) {
+				panel = dev->mode.name;
+				printf("auto-detected panel %s\n", panel);
+				break;
+			}
+		}
+		if (!panel) {
+			panel = displays[0].mode.name;
+			printf("No panel detected: default to %s\n", panel);
+		}
+	} else {
+		for (i = 0; i < ARRAY_SIZE(displays); i++) {
+			if (!strcmp(panel, displays[i].mode.name))
+				break;
+		}
+	}
+	if (i < ARRAY_SIZE(displays)) {
+		ret = ipuv3_fb_init(&displays[i].mode, 0,
+				    displays[i].pixfmt);
+		if (!ret) {
+			displays[i].enable(displays+i);
+			printf("Display: %s (%ux%u)\n",
+			       displays[i].mode.name,
+			       displays[i].mode.xres,
+			       displays[i].mode.yres);
+		} else
+			printf("LCD %s cannot be configured: %d\n",
+			       displays[i].mode.name, ret);
+	} else {
+		printf("unsupported panel %s\n", panel);
+		ret = -EINVAL;
+	}
+	return (0 != ret);
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	int reg;
+
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
+		|MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Turn on HDMI PHY clock */
+	reg = __raw_readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+
+	/* clear HDMI PHY reset */
+	__raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
+		     HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
+
+	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
+	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
+	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+	      |(CHSCCDR_PODF_DIVIDE_BY_3
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlights off until needed */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	gpio_direction_input(LVDS_BACKLIGHT_GP);
+	gpio_direction_input(RGB_BACKLIGHT_GP);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	/* Disable wl1271 For Nitrogen6w */
+	gpio_direction_input(WL12XX_WL_IRQ_GP);
+	gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
+	gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
+
+	imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
+	setup_buttons();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (gpio_get_value(WL12XX_WL_IRQ_GP))
+		puts("Board: Nitrogen6X\n");
+	else
+		puts("Board: SABRE Lite\n");
+
+	return 0;
+}
+
+struct button_key {
+	char const	*name;
+	unsigned	gpnum;
+	char		ident;
+};
+
+static struct button_key const buttons[] = {
+	{"back",	IMX_GPIO_NR(2, 2),	'B'},
+	{"home",	IMX_GPIO_NR(2, 4),	'H'},
+	{"menu",	IMX_GPIO_NR(2, 1),	'M'},
+	{"search",	IMX_GPIO_NR(2, 3),	'S'},
+	{"volup",	IMX_GPIO_NR(7, 13),	'V'},
+	{"voldown",	IMX_GPIO_NR(4, 5),	'v'},
+};
+
+/*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+static int read_keys(char *buf)
+{
+	int i, numpressed = 0;
+	for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+		if (!gpio_get_value(buttons[i].gpnum))
+			buf[numpressed++] = buttons[i].ident;
+	}
+	buf[numpressed] = '\0';
+	return numpressed;
+}
+
+static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char envvalue[ARRAY_SIZE(buttons)+1];
+	int numpressed = read_keys(envvalue);
+	setenv("keybd", envvalue);
+	return numpressed == 0;
+}
+
+U_BOOT_CMD(
+	kbd, 1, 1, do_kbd,
+	"Tests for keypresses, sets 'keybd' environment variable",
+	"Returns 0 (true) to shell if key is pressed."
+);
+
+#ifdef CONFIG_PREBOOT
+static char const kbd_magic_prefix[] = "key_magic";
+static char const kbd_command_prefix[] = "key_cmd";
+
+static void preboot_keys(void)
+{
+	int numpressed;
+	char keypress[ARRAY_SIZE(buttons)+1];
+	numpressed = read_keys(keypress);
+	if (numpressed) {
+		char *kbd_magic_keys = getenv("magic_keys");
+		char *suffix;
+		/*
+		 * loop over all magic keys
+		 */
+		for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+			char *keys;
+			char magic[sizeof(kbd_magic_prefix) + 1];
+			sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+			keys = getenv(magic);
+			if (keys) {
+				if (!strcmp(keys, keypress))
+					break;
+			}
+		}
+		if (*suffix) {
+			char cmd_name[sizeof(kbd_command_prefix) + 1];
+			char *cmd;
+			sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv(cmd_name);
+			if (cmd) {
+				setenv("preboot", cmd);
+				return;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+	preboot_keys();
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 7d03620..d778f63 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -252,6 +252,12 @@  mx6qarm2                     arm         armv7       mx6qarm2            freesca
 mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6		mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
 mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+nitrogen6q                   arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q
+nitrogen6dl                  arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
+nitrogen6s                   arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S
+nitrogen6q2g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q
+nitrogen6dl2g                arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL
+nitrogen6s1g                 arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S
 eco5pk                       arm         armv7       eco5pk              8dtech         omap3
 cm_t35                       arm         armv7       cm_t35              -              omap3
 omap3_overo                  arm         armv7       overo               -              omap3
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 1b20e41..c1ae3d9 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -21,7 +21,6 @@ 
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx6x_pins.h>
 #include <asm/imx-common/iomux-v3.h>
 
 #include "ehci.h"
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
new file mode 100644
index 0000000..ef6089a
--- /dev/null
+++ b/include/configs/nitrogen6x.h
@@ -0,0 +1,284 @@ 
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	3769
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_IMXOTP
+#ifdef CONFIG_CMD_IMXOTP
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE			OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX		0x7F
+#define IMX_OTP_DATA_ERROR_VAL		0xBADABADA
+/* #define IMX_OTPWRITE_ENABLED */
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	       1
+#define CONFIG_BAUDRATE			       115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	       1
+
+#define CONFIG_PREBOOT                 ""
+
+#define CONFIG_LOADADDR			       0x12000000
+#define CONFIG_SYS_TEXT_BASE	       0x17800000
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DRIVE_SATA "sata "
+#else
+#define CONFIG_DRIVE_SATA
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1\0" \
+	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
+		"sf erase 0xc0000 0x2000 && " \
+		"echo restored environment to factory default ; fi\0" \
+	"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
+		"; do " \
+			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+				"for fs in fat ext2 ; do " \
+					"${fs}load " \
+						"${dtype} ${disk}:1 " \
+						"10008000 " \
+						"/6x_bootscript" \
+						"&& source 10008000 ; " \
+				"done ; " \
+			"done ; " \
+		"done; " \
+		"setenv stdout serial,vga ; " \
+		"echo ; echo 6x_bootscript not found ; " \
+		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
+		"echo details at http://boundarydevices.com/6q_bootscript ; " \
+		"setenv stdout serial\0" \
+	"upgradeu=for dtype in sata mmc " CONFIG_DRIVE_TYPES \
+		"; do " \
+		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+		     "for fs in fat ext2 ; do " \
+				"${fs}load ${dtype} ${disk}:1 10008000 " \
+					"/6x_upgrade " \
+					"&& source 10008000 ; " \
+			"done ; " \
+		"done ; " \
+	"done\0" \
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	       1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+
+#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
+#define CONFIG_SYS_HZ		       1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	       1
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+/* #define CONFIG_ENV_IS_IN_MMC */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BMP
+
+#endif	       /* __CONFIG_H */