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[U-Boot,5/6] imx: mx6q DDR3 init: Fix MR0.PPD

Message ID 1359580758-20743-5-git-send-email-benoit.thebaudeau@advansee.com
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Commit Message

Benoît Thébaudeau Jan. 30, 2013, 9:19 p.m. UTC 
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 51f8c35..d50858d 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -126,8 +126,8 @@  DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
+DATA 4 0x021b001c 0x19408030
+DATA 4 0x021b001c 0x19408038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048