Patchwork [U-Boot,03/10] mx23evk: Adjust DRAM control register to use full 128MB of RAM

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Submitter Otavio Salvador
Date Jan. 30, 2013, 12:13 p.m.
Message ID <1359548001-14278-4-git-send-email-otavio@ossystems.com.br>
Download mbox | patch
Permalink /patch/216877/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Otavio Salvador - Jan. 30, 2013, 12:13 p.m.
Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---
 board/freescale/mx23evk/spl_boot.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
Marek Vasut - Jan. 30, 2013, 2:12 p.m.
Dear Otavio Salvador,

> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
> 128MB of RAM.
> 
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

Just enable the full set for all in the generic memory register set (dram_vals)?

> ---
>  board/freescale/mx23evk/spl_boot.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/board/freescale/mx23evk/spl_boot.c
> b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644
> --- a/board/freescale/mx23evk/spl_boot.c
> +++ b/board/freescale/mx23evk/spl_boot.c
> @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
>  		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
>  };
> 
> +#define HW_DRAM_CTL14	(0x38 >> 2)
> +#define CS_MAP		0x3
> +#define INTAREF		0x2
> +#define HW_DRAM_CTL14_CONFIG	(INTAREF << 8 | CS_MAP)
> +
> +void mxs_adjust_memory_params(uint32_t *dram_vals)
> +{
> +	dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
> +}
> +
>  void board_init_ll(void)
>  {
>  	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));

Best regards,
Marek Vasut
Otavio Salvador - Jan. 30, 2013, 3:34 p.m.
On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
> Dear Otavio Salvador,
>
>> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
>> 128MB of RAM.
>>
>> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>
> Just enable the full set for all in the generic memory register set (dram_vals)?

Per datasheet description it shouldn't be done for LQFP; so the safest
setting is to the default we're using as it will work for new boards
and the chip select can be adjusted when need.

>> ---
>>  board/freescale/mx23evk/spl_boot.c | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/board/freescale/mx23evk/spl_boot.c
>> b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644
>> --- a/board/freescale/mx23evk/spl_boot.c
>> +++ b/board/freescale/mx23evk/spl_boot.c
>> @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
>>               (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
>>  };
>>
>> +#define HW_DRAM_CTL14        (0x38 >> 2)
>> +#define CS_MAP               0x3
>> +#define INTAREF              0x2
>> +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP)
>> +
>> +void mxs_adjust_memory_params(uint32_t *dram_vals)
>> +{
>> +     dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
>> +}
>> +
>>  void board_init_ll(void)
>>  {
>>       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
>
> Best regards,
> Marek Vasut



--
Otavio Salvador                             O.S. Systems
E-mail: otavio@ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br
Marek Vasut - Jan. 30, 2013, 3:38 p.m.
Dear Otavio Salvador,

> On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Otavio Salvador,
> > 
> >> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
> >> 128MB of RAM.
> >> 
> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> > 
> > Just enable the full set for all in the generic memory register set
> > (dram_vals)?
> 
> Per datasheet description it shouldn't be done for LQFP;

LQFP package is missing pinmux for the other pins, so that's ok.

> so the safest
> setting is to the default we're using as it will work for new boards
> and the chip select can be adjusted when need.

And since the block inside the CPU is the same, just missing the pinmux, it is 
also safe to enable all CS lines for default operation.

> >> ---
> >> 
> >>  board/freescale/mx23evk/spl_boot.c | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >> 
> >> diff --git a/board/freescale/mx23evk/spl_boot.c
> >> b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644
> >> --- a/board/freescale/mx23evk/spl_boot.c
> >> +++ b/board/freescale/mx23evk/spl_boot.c
> >> @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
> >> 
> >>               (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
> >>  
> >>  };
> >> 
> >> +#define HW_DRAM_CTL14        (0x38 >> 2)
> >> +#define CS_MAP               0x3
> >> +#define INTAREF              0x2
> >> +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP)
> >> +
> >> +void mxs_adjust_memory_params(uint32_t *dram_vals)
> >> +{
> >> +     dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
> >> +}
> >> +
> >> 
> >>  void board_init_ll(void)
> >>  {
> >>  
> >>       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
> > 
> > Best regards,
> > Marek Vasut
> 
> --
> Otavio Salvador                             O.S. Systems
> E-mail: otavio@ossystems.com.br  http://www.ossystems.com.br
> Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Best regards,
Marek Vasut
Otavio Salvador - Jan. 30, 2013, 3:46 p.m.
On Wed, Jan 30, 2013 at 1:38 PM, Marek Vasut <marex@denx.de> wrote:
> Dear Otavio Salvador,
>
>> On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
>> > Dear Otavio Salvador,
>> >
>> >> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
>> >> 128MB of RAM.
>> >>
>> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>> >
>> > Just enable the full set for all in the generic memory register set
>> > (dram_vals)?
>>
>> Per datasheet description it shouldn't be done for LQFP;
>
> LQFP package is missing pinmux for the other pins, so that's ok.
>
>> so the safest
>> setting is to the default we're using as it will work for new boards
>> and the chip select can be adjusted when need.
>
> And since the block inside the CPU is the same, just missing the pinmux, it is
> also safe to enable all CS lines for default operation.

If this is the case why they added the CS selector? The datasheet is
clear about the different setting in BGA and LQFP. I'd prefer if
someone from Freescale could check if it would be safe to enable them
all or not. Fabio? :-)

--
Otavio Salvador                             O.S. Systems
E-mail: otavio@ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br
Marek Vasut - Jan. 30, 2013, 3:55 p.m.
Dear Otavio Salvador,

> On Wed, Jan 30, 2013 at 1:38 PM, Marek Vasut <marex@denx.de> wrote:
> > Dear Otavio Salvador,
> > 
> >> On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
> >> > Dear Otavio Salvador,
> >> > 
> >> >> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of
> >> >> full 128MB of RAM.
> >> >> 
> >> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> >> > 
> >> > Just enable the full set for all in the generic memory register set
> >> > (dram_vals)?
> >> 
> >> Per datasheet description it shouldn't be done for LQFP;
> > 
> > LQFP package is missing pinmux for the other pins, so that's ok.
> > 
> >> so the safest
> >> setting is to the default we're using as it will work for new boards
> >> and the chip select can be adjusted when need.
> > 
> > And since the block inside the CPU is the same, just missing the pinmux,
> > it is also safe to enable all CS lines for default operation.
> 
> If this is the case why they added the CS selector?

CS selector?

> The datasheet is
> clear about the different setting in BGA and LQFP.

It'd be nice if you gave a ref. into the datasheet where I can find such 
information.

> I'd prefer if
> someone from Freescale could check if it would be safe to enable them
> all or not. Fabio? :-)

According to table 12-36 and 37.4 , EMI has two CE lines max (CE0N and CE1N). If 
CE1 is not present on the smaller package, it's not a problem, since whenever 
asserted, the MUX won't let the signal go further. Moreover, the CE line is 
asserted only when particular memory area is accessed.

Thus, CS_MAP shall be 0x3 in default setup.

btw. this patch is misconfiguring INTAREF field which is not documented in the 
commit message.

Best regards,
Marek Vasut
Otavio Salvador - Jan. 30, 2013, 4 p.m.
On Wed, Jan 30, 2013 at 1:55 PM, Marek Vasut <marex@denx.de> wrote:
> Dear Otavio Salvador,
>
>> On Wed, Jan 30, 2013 at 1:38 PM, Marek Vasut <marex@denx.de> wrote:
>> > Dear Otavio Salvador,
>> >
>> >> On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut <marex@denx.de> wrote:
>> >> > Dear Otavio Salvador,
>> >> >
>> >> >> Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of
>> >> >> full 128MB of RAM.
>> >> >>
>> >> >> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>> >> >
>> >> > Just enable the full set for all in the generic memory register set
>> >> > (dram_vals)?
>> >>
>> >> Per datasheet description it shouldn't be done for LQFP;
>> >
>> > LQFP package is missing pinmux for the other pins, so that's ok.
>> >
>> >> so the safest
>> >> setting is to the default we're using as it will work for new boards
>> >> and the chip select can be adjusted when need.
>> >
>> > And since the block inside the CPU is the same, just missing the pinmux,
>> > it is also safe to enable all CS lines for default operation.
>>
>> If this is the case why they added the CS selector?
>
> CS selector?
>
>> The datasheet is
>> clear about the different setting in BGA and LQFP.
>
> It'd be nice if you gave a ref. into the datasheet where I can find such
> information.
>
>> I'd prefer if
>> someone from Freescale could check if it would be safe to enable them
>> all or not. Fabio? :-)
>
> According to table 12-36 and 37.4 , EMI has two CE lines max (CE0N and CE1N). If
> CE1 is not present on the smaller package, it's not a problem, since whenever
> asserted, the MUX won't let the signal go further. Moreover, the CE line is
> asserted only when particular memory area is accessed.
>
> Thus, CS_MAP shall be 0x3 in default setup.
>
> btw. this patch is misconfiguring INTAREF field which is not documented in the
> commit message.

It is not changing the value of it but setting to the same used in
default setup. So I did not include it in commit log.

I will give it a test in mx23_olinuxino and then if it does work fine
I do the change for v2.

--
Otavio Salvador                             O.S. Systems
E-mail: otavio@ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Patch

diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
index 6007433..b6f4e7e 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -98,6 +98,16 @@  const iomux_cfg_t iomux_setup[] = {
 		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
 };
 
+#define HW_DRAM_CTL14	(0x38 >> 2)
+#define CS_MAP		0x3
+#define INTAREF		0x2
+#define HW_DRAM_CTL14_CONFIG	(INTAREF << 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
 void board_init_ll(void)
 {
 	mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));