From patchwork Wed Jan 30 01:40:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 216745 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D8FFF2C0085 for ; Wed, 30 Jan 2013 12:41:36 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753480Ab3A3Blf (ORCPT ); Tue, 29 Jan 2013 20:41:35 -0500 Received: from szxga01-in.huawei.com ([119.145.14.64]:32002 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753215Ab3A3Ble (ORCPT ); Tue, 29 Jan 2013 20:41:34 -0500 Received: from 172.24.2.119 (EHLO szxeml212-edg.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.4-GA FastPath queued) with ESMTP id AWW60151; Wed, 30 Jan 2013 09:41:21 +0800 (CST) Received: from SZXEML408-HUB.china.huawei.com (10.82.67.95) by szxeml212-edg.china.huawei.com (172.24.2.181) with Microsoft SMTP Server (TLS) id 14.1.323.7; Wed, 30 Jan 2013 09:41:18 +0800 Received: from localhost (10.135.76.69) by szxeml408-hub.china.huawei.com (10.82.67.95) with Microsoft SMTP Server id 14.1.323.7; Wed, 30 Jan 2013 09:41:13 +0800 From: Yijing Wang To: Rob Landley , Bjorn Helgaas , Jon Mason CC: , , , Andrew Murray , Joe Lawrence , Randy Dunlap , Hanjun Guo , , Yijing Wang Subject: [PATCH v4] PCI: Document PCIE BUS MPS parameters Date: Wed, 30 Jan 2013 09:40:52 +0800 Message-ID: <1359510052-21360-1-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.11.msysgit.1 MIME-Version: 1.0 X-Originating-IP: [10.135.76.69] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org v0->v1: Update MPS parameters as non-arch and add MRRS description into pcie_bus_perf parameter suggested by Andrew Murray. v1->v2: Update some semantic problems and add MPS and MRRS explanation suggested by Joe Lawrence and Randy Dunlap. v2->v3: Update some semantic problems and the description of pcie_bus_safe and pcie_bus_peer2peer suggested by Bjorn Helgaas. v3->v4: Update pcie_bus_safe description suggested by Jon Mason Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe, pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt. These parameters were introduced by Jon Mason at commit 5f39e6705 and commit b03e7495a8. Signed-off-by: Yijing Wang --- Documentation/kernel-parameters.txt | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 363e348..6ad9b95 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2227,6 +2227,20 @@ bytes respectively. Such letter suffixes can also be entirely omitted. This sorting is done to get a device order compatible with older (<= 2.4) kernels. nobfsort Don't sort PCI devices into breadth-first order. + pcie_bus_tune_off Disable PCIe MPS (Max Payload Size) + tuning and use the BIOS-configured MPS defaults. + pcie_bus_safe Set every device's MPS to the largest MPSS + (Max Payload Size Support) common to all devices + below the root complex. + pcie_bus_perf Configure device MPS to the largest + allowable MPS based on its parent bus. Also set + MRRS (Max Read Request Size) to the largest supported + value (no larger than the MPS that the device or bus + can support) for best performance. + pcie_bus_peer2peer Set every device's MPS to 128B, which + every device is guaranteed to support. This + configuration allows peer-to-peer DMA between any pair + of devices possibly at the cost of reduced performance. cbiosize=nn[KMG] The fixed amount of bus space which is reserved for the CardBus bridge's IO window. The default value is 256 bytes.