From patchwork Tue Jan 29 13:50:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hurugalawadi, Naveen" X-Patchwork-Id: 216534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id F41AA2C008D for ; Wed, 30 Jan 2013 00:50:34 +1100 (EST) Comment: DKIM? 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The patch adds a testcase ands.c which is similar to the adds.c. Please review the patch and let me know if there should be any modifications? Regressed for aarch64-elf on aarch64-4.7-branch. Thanks, Naveen.H.S gcc/ 2013-01-29 Naveen H.S * config/aarch64/aarch64.md (*and3_compare0): New pattern. (*andsi3_compare0_uxtw): New pattern. gcc/testsuite/ 2013-01-29 Naveen H.S * gcc.target/aarch64/ands.c: New. --- gcc/config/aarch64/aarch64.md 2013-01-25 15:52:09.214218793 +0530 +++ gcc/config/aarch64/aarch64.md 2013-01-29 18:51:46.965821291 +0530 @@ -2370,6 +2370,35 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "")]) +(define_insn "*and3_compare0" + [(set (reg:CC CC_REGNUM) + (compare:CC + (and:GPI (match_operand:GPI 1 "register_operand" "%r,r") + (match_operand:GPI 2 "aarch64_logical_operand" "r,")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r,r") + (and:GPI (match_dup 1) (match_dup 2)))] + "" + "ands\\t%0, %1, %2" + [(set_attr "v8type" "logic,logic_imm") + (set_attr "mode" "")] +) + +;; zero_extend version of above +(define_insn "*andsi3_compare0_uxtw" + [(set (reg:CC CC_REGNUM) + (compare:CC + (and:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "aarch64_logical_operand" "r,K")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] + "" + "ands\\t%w0, %w1, %w2" + [(set_attr "v8type" "logic,logic_imm") + (set_attr "mode" "SI")] +) + (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI --- gcc/testsuite/gcc.target/aarch64/ands.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/ands.c 2013-01-29 16:10:23.817675842 +0530 @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int z; +int +foo (int x, int y) +{ + int l = x & y; + if (l == 0) + return 5; + + /* { dg-final { scan-assembler "ands\tw\[0-9\]" } } */ + z = l ; + return 25; +} + +typedef long long s64; + +s64 zz; +s64 +foo2 (s64 x, s64 y) +{ + s64 l = x & y; + if (l < 0) + return 5; + + /* { dg-final { scan-assembler "ands\tx\[0-9\]" } } */ + zz = l ; + return 25; +}