From patchwork Sun Jan 27 22:17:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [2/2] clk: tegra: add ac97 controller clock Date: Sun, 27 Jan 2013 12:17:35 -0000 From: Lucas Stach X-Patchwork-Id: 216069 Message-Id: <1359325055-5160-2-git-send-email-dev@lynxeye.de> To: linux-tegra@vger.kernel.org Cc: Prashant Gaikwad , Stephen Warren AC97 controller clock is hardwired to pll_a_out0. Signed-off-by: Lucas Stach --- drivers/clk/tegra/clk-tegra20.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index f08cffc..1be8c23 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -894,6 +894,14 @@ static void __init tegra20_periph_clk_init(void) struct clk *clk; int i; + /* ac97 */ + clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", + TEGRA_PERIPH_ON_APB, + clk_base, 0, 3, &periph_l_regs, + periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "tegra20-ac97"); + clks[ac97] = clk; + /* apbdma */ clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 0, 34, &periph_h_regs,