From patchwork Sun Jan 27 22:17:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 216069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 190732C0092 for ; Mon, 28 Jan 2013 09:17:44 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756701Ab3A0WRm (ORCPT ); Sun, 27 Jan 2013 17:17:42 -0500 Received: from ns.km20343-01.keymachine.de ([84.19.182.79]:35965 "EHLO km20343-01.keymachine.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756677Ab3A0WRm (ORCPT ); Sun, 27 Jan 2013 17:17:42 -0500 Received: from localhost.localdomain (g231099067.adsl.alicedsl.de [92.231.99.67]) by km20343-01.keymachine.de (Postfix) with ESMTPA id 59B767D42E3; Sun, 27 Jan 2013 23:17:40 +0100 (CET) From: Lucas Stach To: linux-tegra@vger.kernel.org Cc: Prashant Gaikwad , Stephen Warren Subject: [PATCH 2/2] clk: tegra: add ac97 controller clock Date: Sun, 27 Jan 2013 23:17:35 +0100 Message-Id: <1359325055-5160-2-git-send-email-dev@lynxeye.de> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1359325055-5160-1-git-send-email-dev@lynxeye.de> References: <1359325055-5160-1-git-send-email-dev@lynxeye.de> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org AC97 controller clock is hardwired to pll_a_out0. Signed-off-by: Lucas Stach --- drivers/clk/tegra/clk-tegra20.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index f08cffc..1be8c23 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -894,6 +894,14 @@ static void __init tegra20_periph_clk_init(void) struct clk *clk; int i; + /* ac97 */ + clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", + TEGRA_PERIPH_ON_APB, + clk_base, 0, 3, &periph_l_regs, + periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "tegra20-ac97"); + clks[ac97] = clk; + /* apbdma */ clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 0, 34, &periph_h_regs,