From patchwork Sun Jan 27 10:39:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kirsher, Jeffrey T" X-Patchwork-Id: 215982 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5C8BE2C0090 for ; Sun, 27 Jan 2013 21:40:37 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756608Ab3A0Kkf (ORCPT ); Sun, 27 Jan 2013 05:40:35 -0500 Received: from mga11.intel.com ([192.55.52.93]:26342 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756532Ab3A0KkD (ORCPT ); Sun, 27 Jan 2013 05:40:03 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 27 Jan 2013 02:39:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,546,1355126400"; d="scan'208";a="278911513" Received: from unknown (HELO jtkirshe-mobl.amr.corp.intel.com) ([10.255.15.46]) by fmsmga001.fm.intel.com with ESMTP; 27 Jan 2013 02:39:59 -0800 From: Jeff Kirsher To: davem@davemloft.net Cc: Bruce Allan , netdev@vger.kernel.org, gospo@redhat.com, sassmann@redhat.com, Jeff Kirsher Subject: [net-next 09/14] e1000e: fix PHY init workarounds for i217/i218 Date: Sun, 27 Jan 2013 02:39:48 -0800 Message-Id: <1359283193-2043-10-git-send-email-jeffrey.t.kirsher@intel.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1359283193-2043-1-git-send-email-jeffrey.t.kirsher@intel.com> References: <1359283193-2043-1-git-send-email-jeffrey.t.kirsher@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bruce Allan Toggling the LANPHYPC Value bit cycles the power on the PHY and sets it back to power-on defaults. This includes setting it's MAC-PHY messaging mode to use the PCIe-like interconnect, so the MAC must also be set back from SMBus mode to PCIe mode otherwise the PHY can be inaccessible. Signed-off-by: Bruce Allan Tested-by: Jeff Pieper Signed-off-by: Jeff Kirsher --- drivers/net/ethernet/intel/e1000e/ich8lan.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c index e0f41f0..3f3477f 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.c +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c @@ -426,6 +426,15 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; ew32(FEXTNVM3, mac_reg); + if (hw->mac.type == e1000_pch_lpt) { + /* Toggling LANPHYPC brings the PHY out of SMBus mode + * So ensure that the MAC is also out of SMBus mode + */ + mac_reg = er32(CTRL_EXT); + mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; + ew32(CTRL_EXT, mac_reg); + } + /* Toggle LANPHYPC Value bit */ mac_reg = er32(CTRL); mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;