From patchwork Fri Jan 25 12:53:00 2013
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [17/21] openpic: fix timer address decoding
Date: Fri, 25 Jan 2013 02:53:00 -0000
From: Alexander Graf <agraf@suse.de>
X-Patchwork-Id: 215768
Message-Id: <1359118384-9555-18-git-send-email-agraf@suse.de>
To: qemu-ppc@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>, Scott Wood <scottwood@freescale.com>, 
 qemu-devel <qemu-devel@nongnu.org>,
 =?utf-8?q?Aur=C3=A9lien=20Jarno?= <aurelien@aurel32.net>

From: Scott Wood <scottwood@freescale.com>

The timer memory range begins at 0x10f0, so that address 0x1120 shows
up as 0x30, 0x1130 shows up as 0x40, etc.  However, the address
decoding (other than TFRR) is not adjusted for this, causing the
wrong registers to be accessed.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

---
hw/openpic.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index a4488c2..0a4379f 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -792,19 +792,23 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
     OpenPICState *opp = opaque;
     int idx;
 
+    addr += 0x10f0;
+
     DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
             __func__, addr, val);
     if (addr & 0xF) {
         return;
     }
-    idx = (addr >> 6) & 0x3;
-    addr = addr & 0x30;
 
-    if (addr == 0x0) {
+    if (addr == 0x10f0) {
         /* TFRR */
         opp->tfrr = val;
         return;
     }
+
+    idx = (addr >> 6) & 0x3;
+    addr = addr & 0x30;
+
     switch (addr & 0x30) {
     case 0x00: /* TCCR */
         break;