From patchwork Fri Jan 25 12:53:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [19/21] PPC: e500: fix mpic_iack address Date: Fri, 25 Jan 2013 02:53:02 -0000 From: Alexander Graf X-Patchwork-Id: 215738 Message-Id: <1359118384-9555-20-git-send-email-agraf@suse.de> To: qemu-ppc@nongnu.org Cc: Blue Swirl , Scott Wood , qemu-devel , =?utf-8?q?Aur=C3=A9lien=20Jarno?= From: Scott Wood MPIC+0xa0 is IACK for the current CPU. MPIC+0x200a0 is IACK for CPU 0. This fix allows EPR to work with an SMP target. Signed-off-by: Scott Wood Signed-off-by: Alexander Graf --- hw/ppc/e500.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9ccf4d1..530f929 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -505,7 +505,7 @@ void ppce500_init(PPCE500Params *params) irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; env->mpic_iack = MPC8544_CCSRBAR_BASE + - MPC8544_MPIC_REGS_OFFSET + 0x200A0; + MPC8544_MPIC_REGS_OFFSET + 0xa0; ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);