Patchwork [v3] PCI: Document PCIE BUS MPS parameters

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Submitter Yijing Wang
Date Jan. 25, 2013, 9:36 a.m.
Message ID <1359106615-17544-1-git-send-email-wangyijing@huawei.com>
Download mbox | patch
Permalink /patch/215599/
State Superseded
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Comments

Yijing Wang - Jan. 25, 2013, 9:36 a.m.
v0->v1: Update MPS parameters as non-arch and add MRRS
		description into pcie_bus_perf parameter suggested
		by Andrew Murray.
v1->v2: Update some semantic problems and add MPS and MRRS
		explanation suggested by Joe Lawrence and Randy Dunlap.
v2->v3: Update some semantic problems and the description
		of pcie_bus_safe and pcie_bus_peer2peer suggested
		by Bjorn Helgaas.

Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
These parameters were introduced by Jon Mason <mason@myri.com> at
commit 5f39e6705 and commit b03e7495a8.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
 Documentation/kernel-parameters.txt |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
Jon Mason - Jan. 29, 2013, 5 a.m.
On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
> v0->v1: Update MPS parameters as non-arch and add MRRS
>                 description into pcie_bus_perf parameter suggested
>                 by Andrew Murray.
> v1->v2: Update some semantic problems and add MPS and MRRS
>                 explanation suggested by Joe Lawrence and Randy Dunlap.
> v2->v3: Update some semantic problems and the description
>                 of pcie_bus_safe and pcie_bus_peer2peer suggested
>                 by Bjorn Helgaas.
>
> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
> These parameters were introduced by Jon Mason <mason@myri.com> at
> commit 5f39e6705 and commit b03e7495a8.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
>  Documentation/kernel-parameters.txt |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
> index 363e348..2997df2 100644
> --- a/Documentation/kernel-parameters.txt
> +++ b/Documentation/kernel-parameters.txt
> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>                                 This sorting is done to get a device
>                                 order compatible with older (<= 2.4) kernels.
>                 nobfsort        Don't sort PCI devices into breadth-first order.
> +               pcie_bus_tune_off       Disable PCIe MPS (Max Payload Size)
> +                               tuning and use the BIOS-configured MPS defaults.
> +               pcie_bus_safe   Use the smallest supported MPS of any device
> +                               below a root complex.

This isn't correct.  It should be something like "The largest MPS
common to all devices below the root complex".

> +               pcie_bus_perf   Configure device MPS to the largest
> +                               allowable MPS based on its parent bus. Also set
> +                               MRRS (Max Read Request Size) to the largest supported
> +                               value (no larger than the MPS that the device or bus
> +                               can support) for best performance.
> +               pcie_bus_peer2peer      Set every device's MPS to 128B, which
> +                               every device is guaranteed to support. This
> +                               configuration allows peer-to-peer DMA between any pair
> +                               of devices possibly at the cost of reduced performance.
>                 cbiosize=nn[KMG]        The fixed amount of bus space which is
>                                 reserved for the CardBus bridge's IO window.
>                                 The default value is 256 bytes.
> --
> 1.7.1
>
>
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Yijing Wang - Jan. 29, 2013, 6:09 a.m.
On 2013/1/29 13:00, Jon Mason wrote:
> On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
>> v0->v1: Update MPS parameters as non-arch and add MRRS
>>                 description into pcie_bus_perf parameter suggested
>>                 by Andrew Murray.
>> v1->v2: Update some semantic problems and add MPS and MRRS
>>                 explanation suggested by Joe Lawrence and Randy Dunlap.
>> v2->v3: Update some semantic problems and the description
>>                 of pcie_bus_safe and pcie_bus_peer2peer suggested
>>                 by Bjorn Helgaas.
>>
>> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
>> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
>> These parameters were introduced by Jon Mason <mason@myri.com> at
>> commit 5f39e6705 and commit b03e7495a8.
>>
>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>> ---
>>  Documentation/kernel-parameters.txt |   13 +++++++++++++
>>  1 files changed, 13 insertions(+), 0 deletions(-)
>>
>> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
>> index 363e348..2997df2 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation/kernel-parameters.txt
>> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>>                                 This sorting is done to get a device
>>                                 order compatible with older (<= 2.4) kernels.
>>                 nobfsort        Don't sort PCI devices into breadth-first order.
>> +               pcie_bus_tune_off       Disable PCIe MPS (Max Payload Size)
>> +                               tuning and use the BIOS-configured MPS defaults.
>> +               pcie_bus_safe   Use the smallest supported MPS of any device
>> +                               below a root complex.
> 
> This isn't correct.  It should be something like "The largest MPS
> common to all devices below the root complex".

Hi Jon,
   Thanks for your review and comment!
What about "Set every device's MPS to the largest MPSS (Max Payload Size Support)
common to all devices below the root complex" ?

> 
>> +               pcie_bus_perf   Configure device MPS to the largest
>> +                               allowable MPS based on its parent bus. Also set
>> +                               MRRS (Max Read Request Size) to the largest supported
>> +                               value (no larger than the MPS that the device or bus
>> +                               can support) for best performance.
>> +               pcie_bus_peer2peer      Set every device's MPS to 128B, which
>> +                               every device is guaranteed to support. This
>> +                               configuration allows peer-to-peer DMA between any pair
>> +                               of devices possibly at the cost of reduced performance.
>>                 cbiosize=nn[KMG]        The fixed amount of bus space which is
>>                                 reserved for the CardBus bridge's IO window.
>>                                 The default value is 256 bytes.
>> --
>> 1.7.1
>>
>>
> 
> .
>
Jon Mason - Jan. 29, 2013, 2:18 p.m.
On Mon, Jan 28, 2013 at 11:09 PM, Yijing Wang <wangyijing@huawei.com> wrote:
> On 2013/1/29 13:00, Jon Mason wrote:
>> On Fri, Jan 25, 2013 at 2:36 AM, Yijing Wang <wangyijing@huawei.com> wrote:
>>> v0->v1: Update MPS parameters as non-arch and add MRRS
>>>                 description into pcie_bus_perf parameter suggested
>>>                 by Andrew Murray.
>>> v1->v2: Update some semantic problems and add MPS and MRRS
>>>                 explanation suggested by Joe Lawrence and Randy Dunlap.
>>> v2->v3: Update some semantic problems and the description
>>>                 of pcie_bus_safe and pcie_bus_peer2peer suggested
>>>                 by Bjorn Helgaas.
>>>
>>> Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
>>> pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
>>> These parameters were introduced by Jon Mason <mason@myri.com> at
>>> commit 5f39e6705 and commit b03e7495a8.
>>>
>>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>>> ---
>>>  Documentation/kernel-parameters.txt |   13 +++++++++++++
>>>  1 files changed, 13 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
>>> index 363e348..2997df2 100644
>>> --- a/Documentation/kernel-parameters.txt
>>> +++ b/Documentation/kernel-parameters.txt
>>> @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>>>                                 This sorting is done to get a device
>>>                                 order compatible with older (<= 2.4) kernels.
>>>                 nobfsort        Don't sort PCI devices into breadth-first order.
>>> +               pcie_bus_tune_off       Disable PCIe MPS (Max Payload Size)
>>> +                               tuning and use the BIOS-configured MPS defaults.
>>> +               pcie_bus_safe   Use the smallest supported MPS of any device
>>> +                               below a root complex.
>>
>> This isn't correct.  It should be something like "The largest MPS
>> common to all devices below the root complex".
>
> Hi Jon,
>    Thanks for your review and comment!
> What about "Set every device's MPS to the largest MPSS (Max Payload Size Support)
> common to all devices below the root complex" ?

Sounds great!  Thanks so much for documenting this.

>
>>
>>> +               pcie_bus_perf   Configure device MPS to the largest
>>> +                               allowable MPS based on its parent bus. Also set
>>> +                               MRRS (Max Read Request Size) to the largest supported
>>> +                               value (no larger than the MPS that the device or bus
>>> +                               can support) for best performance.
>>> +               pcie_bus_peer2peer      Set every device's MPS to 128B, which
>>> +                               every device is guaranteed to support. This
>>> +                               configuration allows peer-to-peer DMA between any pair
>>> +                               of devices possibly at the cost of reduced performance.
>>>                 cbiosize=nn[KMG]        The fixed amount of bus space which is
>>>                                 reserved for the CardBus bridge's IO window.
>>>                                 The default value is 256 bytes.
>>> --
>>> 1.7.1
>>>
>>>
>>
>> .
>>
>
>
> --
> Thanks!
> Yijing
>
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Patch

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 363e348..2997df2 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2227,6 +2227,19 @@  bytes respectively. Such letter suffixes can also be entirely omitted.
 				This sorting is done to get a device
 				order compatible with older (<= 2.4) kernels.
 		nobfsort	Don't sort PCI devices into breadth-first order.
+		pcie_bus_tune_off	Disable PCIe MPS (Max Payload Size)
+				tuning and use the BIOS-configured MPS defaults.
+		pcie_bus_safe	Use the smallest supported MPS of any device
+				below a root complex.
+		pcie_bus_perf	Configure device MPS to the largest
+				allowable MPS based on its parent bus. Also set
+				MRRS (Max Read Request Size) to the largest supported
+				value (no larger than the MPS that the device or bus
+				can support) for best performance.
+		pcie_bus_peer2peer	Set every device's MPS to 128B, which
+				every device is guaranteed to support. This
+				configuration allows peer-to-peer DMA between any pair
+				of devices possibly at the cost of reduced performance.
 		cbiosize=nn[KMG]	The fixed amount of bus space which is
 				reserved for the CardBus bridge's IO window.
 				The default value is 256 bytes.