From patchwork Fri Jan 25 01:00:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [PATCHv1,for,soc,4/5] arm: Add v7_invalidate_l1 to cache-v7.S Date: Thu, 24 Jan 2013 15:00:32 -0000 From: dinguyen@altera.com X-Patchwork-Id: 215521 Message-Id: <1359075633-13502-5-git-send-email-dinguyen@altera.com> To: Cc: Arnd Bergmann , Stephen Warren , Pavel Machek , Magnus Damm , Rob Herring , Simon Horman , linux-arm-kernel@lists.infradead.org, Sascha Hauer , Olof Johansson , Thomas Gleixner , Dinh Nguyen From: Dinh Nguyen mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen Cc: Arnd Bergmann Cc: Russell King Cc: Olof Johansson Cc: Thomas Gleixner Cc: Rob Herring Cc: Sascha Hauer Cc: Simon Horman Cc: Magnus Damm Cc: Stephen Warren Cc: Pavel Machek Acked-by: Simon Horman Tested-by: Pavel Machek Reviewed-by: Pavel Machek --- arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++++++++++++++ 4 files changed, 47 insertions(+), 138 deletions(-) diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb..921fc15 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -17,53 +17,6 @@ .section ".text.head", "ax" -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<