Patchwork [committed] Fix memory constraints in *and<mode>3_mips16

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Submitter Richard Sandiford
Date Jan. 24, 2013, 5:46 p.m.
Message ID <87sj5qmq26.fsf@talisman.default>
Download mbox | patch
Permalink /patch/215458/
State New
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Comments

Richard Sandiford - Jan. 24, 2013, 5:46 p.m.
Like LWU, MIPS16 LBU and LHU only allow offset(base) addresses,
so they should use "W" rather than "o" as the memory constraint.
This fixes g++.dg/torture/vshuf-v8hi.C on mips64el-linux-gnu,
where the constraints matched a PC-relative address instead.

Tested on mips64el-linux-gnu and applied.

Richard


gcc/
	* config/mips/mips.md (*and<mode>3_mips16): Use the "W" constraint
	for the first two alternatives.

Patch

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	2013-01-12 10:13:07.000000000 +0000
+++ gcc/config/mips/mips.md	2013-01-24 09:20:24.128211222 +0000
@@ -2898,7 +2898,7 @@  (define_insn "*and<mode>3"
 
 (define_insn "*and<mode>3_mips16"
   [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
-	(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
+	(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
 		 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
   "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
 {